- Email: Must_Login
- Registered on: 09/19/2008
- Last connection: 09/19/2011
Reported issues: 4
- 03:08 pm Verilog-Perl Using: RE: Parsing Verilog widths correctly
- Yes, the parameter is declared above the module declaration and as you state is legal in SV but is not normal...
- 11:11 pm Verilog-Perl Using: RE: Parsing Verilog widths correctly
- I am experiencing a similar issue. But in this case the expression is more complicated like:
- 02:37 pm Verilog-Perl Issue #66: Module.pm ports_ordered() seems to return an array of port names and not references.
- Sounds fine. Thanks once again.
- 08:53 pm Verilog-Perl Issue #66 (Closed): Module.pm ports_ordered() seems to return an array of port names and not refe...
- I'm not sure if it's me or my interpretation of the docs.
From Modules.pm :...
- 03:05 am Verilog-Perl Patch #39 (Closed): Support For package item parameter declaration
- This one is iffy. I created a quick patch to support a module I have with package scoped parameters....
- 07:26 pm Verilog-Perl Patch #34 (Closed): timeunits declaration and lifetime on module declarations
- We have some SV code that uses timeunits and timeprecision.
I think I have added timeunits/timeprecision in to the...
- 04:46 pm Verilog-Perl Patch #33 (Closed): Adding feature for case modifiers in SV
- A buddy here is trying to use the sigparser on some SV code that uses 'unique case' modifiers.
I have modified the l...
- 03:52 pm Verilog-Perl Using: RE: backtick directives.
- Here is my code fragment:...
- Hello, I recently upgraded to version 3.041 of Verilog-Perl from a very old version.
My scripts now report errors on...
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