Veripool

09/19/2011

03:08 pm Verilog-Perl Using: RE: Parsing Verilog widths correctly

Yes, the parameter is declared above the module declaration and as you state is legal in SV but is not normal...
So,...

09/16/2011

11:11 pm Verilog-Perl Using: RE: Parsing Verilog widths correctly

I am experiencing a similar issue. But in this case the expression is more complicated like:
WIDTH-1
where width...

02/17/2009

02:37 pm Verilog-Perl Issue #66: Module.pm ports_ordered() seems to return an array of port names and not references.

Sounds fine. Thanks once again.

02/16/2009

08:53 pm Verilog-Perl Issue #66 (Closed): Module.pm ports_ordered() seems to return an array of port names and not refe...

I'm not sure if it's me or my interpretation of the docs.
From Modules.pm :...

10/23/2008

03:05 am Verilog-Perl Patch #39 (Closed): Support For package item parameter declaration

This one is iffy. I created a quick patch to support a module I have with package scoped parameters....

10/13/2008

07:26 pm Verilog-Perl Patch #34 (Closed): timeunits declaration and lifetime on module declarations

We have some SV code that uses timeunits and timeprecision.
I think I have added timeunits/timeprecision in to the...

10/10/2008

04:46 pm Verilog-Perl Patch #33 (Closed): Adding feature for case modifiers in SV

A buddy here is trying to use the sigparser on some SV code that uses 'unique case' modifiers.
I have modified the l...

09/22/2008

03:52 pm Verilog-Perl Using: RE: backtick directives.

Here is my code fragment:...

09/19/2008

06:08 pm Verilog-Perl Using: backtick directives.

Hello, I recently upgraded to version 3.041 of Verilog-Perl from a very old version.
My scripts now report errors on...