Veripool

05/21/2012

02:10 pm Verilator Issue #517: Constant expression in generated block index not recognized

Investigating further, the problem is that this is a very early pass. So in fact even a plain constant parameter will...

12:50 pm Verilator Issue #517 (Feature): Constant expression in generated block index not recognized

The following code fails to recognize the constant expression used as index into an array of generated module instanc...

12:23 pm Verilator Patch #515: Test for System Verilog enumeration methods

Please pull an updated version from https://github.com/jeremybennett/verilator/tree/sv-enum-test.
The intention wa...

05/16/2012

04:35 pm Verilator Patch #515 (Closed): Test for System Verilog enumeration methods

System Verilog provides a set of methods for operating on enumerations. This new test, @t_sv_enum_type_methods.pl@, e...

11:08 am Verilator Patch #473: Set of SystemVerilog tests

I've done some more work on the enum, and will submit a separate issue with a new test to cover some of the enum oper...

05/15/2012

02:26 pm Verilator Issue #514 (Closed): Tristate causes error (in graph, not converted)

Probably a result of recent upgrades to tristate handling, this reportedly worked in the past....

05/10/2012

03:03 pm Verilator Issue #513 (Resolved): Loop causes internal error

The following code has a loop dependency between the first two always blocks. It should execute to completion on the ...

07:14 am Verilator Issue #509: Better error when illegal bit select of array

Thanks for the clarification. I had misread section 7.4.3 of the IEEE 1800-2009. This sort of assignment is only perm...

05/08/2012

11:20 am Verilator Issue #510 (Resolved): Error with unsized elements in tristate select

The following code fails:...

07:56 am Verilator Issue #508: Bit select of constant fails

I should have added that if I change the declaration of b to...