Veripool

01/09/2011

04:14 pm Verilog-Perl Using: error with multiple begin/end in the same generate loop

I was trying to read in a file (code re-use) and got an error.
the file had structure such as
generate
begin...

10/12/2010

07:23 pm Verilog-Perl General: Use as code obfuscator?

Without getting in to a long explanation, I am looking for a way to obfuscate the names in a design.. I had been cons...

08/16/2010

03:15 pm Verilog-Perl Using: RE: how to save a modified file?

Filed... Issue #278

03:15 pm Verilog-Perl Issue #278 (Closed): verilog text does not print port direction for V2001 input code

Reading in a Verilog 2001 file.. just the top level module (not its sub modules)
mod->dump shows that that ports a...

02:13 pm Verilog-Perl Using: RE: how to save a modified file?

netlist->dump shows the list of ports with directions.
input file has
module s0a (
output wire ...

02:04 pm Verilog-Perl Using: RE: How to create new pin/port ?

ah .. that makes total sense.. thanks!

01:32 pm Verilog-Perl Using: How to create new pin/port ?

trying to add a connection from the top level down thru several levels.
So its a matter of walking down the hierar...

01:20 pm Verilog-Perl Using: RE: how to save a modified file?

Couple of questions
a) my source file was Verilog-2001 with ANSI-style declarations... when I
open (OUT...

08/15/2010

08:00 pm Verilog-Perl Using: how to save a modified file?

In the docs I see how to read a file, and I see that I could add a port to a module/instance, but I don't see how to ...

07/12/2010

08:28 pm Verilog-Perl Using: How to access cell type?

I see no method on cell to get the module/cell type, only the name given when instantiated?
If I print $cell->dump...