Veripool

04/10/2012

11:32 am Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd

I noticed that also (but only yesterday). I'll fix that and resubmit. thanks!

04/03/2012

03:42 pm Verilog-mode Using AUTOs: AUTOTIEOFF - include instead of ignore

Hi,
I found that I needed to "include" a group of signals for AUTOTIEOFF, rather
than ignore them, and after spen...

03:22 pm Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd

I made a small set of changes which solve "my problem" (as in, "works for me!" :-) with systemverilog constraints.
I...

01/27/2012

10:52 pm Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd

wow. the html (or php?) code "displayer" really mangled that code. That's not at all what I pasted.
I'll try and...

10:50 pm Verilog-mode Issue #433 (New): indenting for some forms of SystemVerilog constraints is wrong/odd

indentation for several different forms of SV constraints is wrong or odd;
specifically, empty constraints are odd, ...

10/01/2010

01:37 pm Verilator Usage: RE: clocks/signsla generated in top level .cpp don't "change" in waveforms

Adding "public_flat_rw @(xxx)" to the input clocks & reset worked. thanks!
I only do one eval() after each cycle ...

12:36 pm Verilator Usage: clocks/signsla generated in top level .cpp don't "change" in waveforms

I've got a top level .cpp program which controls the simulation. It generates
multiple clocks and resets and feeds ...

09/28/2010

01:00 pm Verilator Issue #289 (Closed): incorrect source file name in error message after include

I have some, ahem, top level .v files which include other .v files
I noticed that if there is a syntax error in on...

07/21/2010

11:45 am Verilator Usage: _FILE_OFFSET_BITS=64? fwrite stops at 2gb

Has anyone tried building verilator with _FILE_OFFSET_BITS=64?
p. I have a sim which generates a log file with fwr...