- Email: Must_Login
- Registered on: 07/21/2010
- Last connection: 04/10/2012
Reported issues: 2
- 11:32 am Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
- I noticed that also (but only yesterday). I'll fix that and resubmit. thanks!
I found that I needed to "include" a group of signals for AUTOTIEOFF, rather
than ignore them, and after spen...
- 03:22 pm Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
- I made a small set of changes which solve "my problem" (as in, "works for me!" :-) with systemverilog constraints.
- 10:52 pm Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
- wow. the html (or php?) code "displayer" really mangled that code. That's not at all what I pasted.
I'll try and...
- 10:50 pm Verilog-mode Issue #433 (New): indenting for some forms of SystemVerilog constraints is wrong/odd
- indentation for several different forms of SV constraints is wrong or odd;
specifically, empty constraints are odd, ...
- 01:37 pm Verilator Usage: RE: clocks/signsla generated in top level .cpp don't "change" in waveforms
- Adding "public_flat_rw @(xxx)" to the input clocks & reset worked. thanks!
I only do one eval() after each cycle ...
- I've got a top level .cpp program which controls the simulation. It generates
multiple clocks and resets and feeds ...
- 01:00 pm Verilator Issue #289 (Closed): incorrect source file name in error message after include
- I have some, ahem, top level .v files which include other .v files
I noticed that if there is a syntax error in on...
- Has anyone tried building verilator with _FILE_OFFSET_BITS=64?
p. I have a sim which generates a log file with fwr...
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