Veripool

02/02/2013

01:51 am Verilator Issue #609: error on array port connection

Here is modified test from regress:...

02/01/2013

09:55 pm Verilator Issue #609 (Closed): error on array port connection

RTL:...

01/15/2013

10:40 pm Verilator Issue #595: Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch

The latest version in git has the problem:...

08:17 pm Verilator Issue #595: Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch

Your test case is a valid case of incorrect RTL that causes internal verilator error (and I think should be addressed...

01/04/2013

12:05 am Verilator Issue #595: Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch

One more thing: there is a simple workaround for this issue:...

01/03/2013

11:53 pm Verilator Issue #595: Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch

Not sure why you are saying about unpacked array. Everything is packed in this case.
flop is defined as:...

12/22/2012

03:07 am Verilator Issue #595 (Closed): Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch

RTL:
typedef logic [40-1:0] addr_t;
logic [$clog2($bits(addr_t))-1:0] shift,
...

11/30/2012

06:29 pm Verilator Issue #584: pure virtual method called/seg. fault

You are right - it works after bug583 fix.

04:47 am Verilator Issue #584 (Duplicate): pure virtual method called/seg. fault

The same RTL compiles with verilator 3.841 w/o problem.
However, the latest version in git fails.
Running regul...

08/10/2012

06:11 am Verilator Issue #544: Support associative arrays

Could you explain a little bit what needs to be done for this? I am assuming backend implementation would use an exis...