Veripool

12/09/2010

07:58 pm Verilog-Perl Using: Parsing Verilog widths correctly

Hi,
I'm having the same issue as a previous user who had filed a bug (about 3 years ago: Here is a link to the fix...

06:37 pm Verilog-Perl Using: RE: Syntax Errors using Packed Structures

Thanks for the info. I was trying to parse it without including the file, but I guess I have to include it.
Thanks...

06:25 pm Verilog-Perl Using: Syntax Errors using Packed Structures

I'm trying to parse a standalone RTL file which has the following line of code in it:
> dps_t dps_a, dps_b, dps_c;...