[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Papers

Mike Denio

  • Email: Must_Login
  • Registered on: 10/07/2011
  • Last connection: 03/15/2012

Activity

Reported issues: 2

03/15/2012

09:50 pm Verilator Issue #457: Problem with simple clock gating
Thanks. That worked on the simple test. I can try it on the actual project tomorrow.
Is this something that I shou...
09:11 pm Verilator Issue #457: Problem with simple clock gating
I just noticed. It appears you have to build it with tracing enabled or the entire function is optimized out.
09:05 pm Verilator Issue #457: Problem with simple clock gating
I'm attaching the .v file. It didn't paste in well...
09:03 pm Verilator Issue #457 (NoFixNeeded): Problem with simple clock gating
I'm creating a derrived clock through a very simple clock gate, but the derrived clock is being treated like a delaye...

10/21/2011

12:48 pm Verilator Usage: RE: Tracing back a Segmentation Fault
Thanks for the help on this. I didn't see the entry in the *final.tree file, and I was never able to create a simplif...

10/07/2011

09:56 pm Verilator Issue #398: DPI-C issue with 64 bit data types when compiled on a 64-bit linux machine
Now that I posted it, my proposed solution won't work because the caller is expecting to pass in a type of QData. Cod...
09:47 pm Verilator Issue #398 (Closed): DPI-C issue with 64 bit data types when compiled on a 64-bit linux machine
The following import statement has a problem.
import "DPI-C" task CMRead64(input int regnum, input int address, ou...
02:07 pm Verilator Usage: Tracing back a Segmentation Fault
I ran a design through Verilator, and the resulting code gets a segmentation fault. The reason is that in the functio...

Also available in: Atom