Veripool

01/23/2009

09:03 pm Verilator Issue #56 (Closed): Inout signals within modules don't propogate correctly.

Suppose you have a child module with an input and output signal. The parent only has an inout signal, and uses logic...

01/22/2009

08:31 pm Verilator Issue #51: Mixing tristate and low-Z drivers. Error Msg unclear.

Here is a simple patch that adds the module and signal name of the current signal causing the problem.

04:37 pm Verilator Usage: RE: Raising the debug level.

That fixed perfectly the logging issue.
Thanks!

01/21/2009

07:52 pm Verilator Issue #51 (Resolved): Mixing tristate and low-Z drivers. Error Msg unclear.

When you get this Error message, there is no additional information that tells you the name of the signal, the file, ...

07:43 pm Verilator Development: RE: TriState Implementation

Maybe I shouldn't file a bug until we look it up in a spec somewhere. It seems like it should work though. We're us...

07:31 pm Verilator Development: TriState Implementation

Suppose I have two modules which have inout data for a wire.
Verilator will compile the following:...

01/20/2009

10:55 pm Verilator Usage: RE: Raising the debug level.

I see what you meant now. I was using Lane's RPM build and hadn't built my own version yet. I'll recompile. Too ba...

10:44 pm Verilator Usage: RE: Raising the debug level.

I'm not getting as far as verilated classes yet. Verilator bailes on the tristate error so I'm trying to see which i...

09:59 pm Verilator Usage: Raising the debug level.

Browsing around in the verilator source, I see UINFO usage with different debug levels. I can't seem to find the com...