- Email: Must_Login
- Registered on: 01/11/2012
- Last connection: 06/07/2013
Reported issues: 0
- 10:11 am Verilator Development: RE: Build time improvements suggestion
- Dear Krzysztof
Can you please send me the SystemC project and I will return it organized as an Eclipse project?
- Dear all,
I have a design located in two folders:
1. Folder 1 includes: top_module and 5 modules. The path is /ho...
- 04:00 pm Verilator Development: RE: More errors
- Dear Sir/Mrs.
The command we gave is:
verilator_bin -sc -O0 --language 1364-2005 -DHAS_DEBUG '-DTEST_FILE=../pacobl...
- 03:28 pm Verilator Development: RE: More errors
- THanks. But this is the real error
%Error: verilator: No Input Verilog file specified on command line, see verilat...
Script started on Thu 09 Feb 2012 05:02:41 PM IST
%Error: Invalid Option: --top-moule
%Error: Command Failed /usr...
We want to do:
verilator -sc -O0 --language 1364-2005 --top-module pacoblazeSM_4XCPU_tb.v -DHAS_DEBUG...
- 03:50 pm Verilator Development: RE: Top Module
- Dear Wilson,
Thanks for your answer. However, the case is that MOdule A instntiate Module B.
- dear sir/Mrs. We wnat to compile a design composed of two modules and roduce SystemC files.
Here is the error messag...
- dear All,
suppose we have a design composed of files A,B and C where A is the top level.
Modules in files B and C ...
- Dear All,
I want to generate a clock pulse. In verilog we do it:
always #(clock_time/2) clk= ~clk
The code is...
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