Veripool

02/23/2012

09:22 am Verilator Usage: Paths

Dear all,
I have a design located in two folders:
1. Folder 1 includes: top_module and 5 modules. The path is /ho...

02/09/2012

04:00 pm Verilator Development: RE: More errors

Dear Sir/Mrs.
The command we gave is:
verilator_bin -sc -O0 --language 1364-2005 -DHAS_DEBUG '-DTEST_FILE=../pacobl...

03:28 pm Verilator Development: RE: More errors

THanks. But this is the real error
%Error: verilator: No Input Verilog file specified on command line, see verilat...

03:10 pm Verilator Development: More errors

Script started on Thu 09 Feb 2012 05:02:41 PM IST
%Error: Invalid Option: --top-moule
%Error: Command Failed /usr...

08:21 am Verilator Development: OPtion -y in verilator

Dear All,
We want to do:
verilator -sc -O0 --language 1364-2005 --top-module pacoblazeSM_4XCPU_tb.v -DHAS_DEBUG...

02/07/2012

03:50 pm Verilator Development: RE: Top Module

Dear Wilson,
Thanks for your answer. However, the case is that MOdule A instntiate Module B.
Best regrdas,
Ye...

03:04 pm Verilator Development: Top Module

dear sir/Mrs. We wnat to compile a design composed of two modules and roduce SystemC files.
Here is the error messag...

02/06/2012

01:15 pm Verilator Development: Top level

dear All,
suppose we have a design composed of files A,B and C where A is the top level.
Modules in files B and C ...

11:07 am Verilator Development: Clock generator

Dear All,
I want to generate a clock pulse. In verilog we do it:
always #(clock_time/2) clk= ~clk
The code is...

01/23/2012

12:38 pm Verilator Usage: RE: Include file

Dear Wilson,
Thanks for the first answer.
What about the language construct PARAMETER?
Thanks,
Yehuda