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Brian Cassell

  • Email: Must_Login
  • Registered on: 04/09/2009
  • Last connection: 03/23/2012

Activity

Reported issues: 0

03/23/2012

10:39 pm Verilog-mode Using AUTOs: RE: Pragmas to disable Indentation for regions of code
That's not exactly what I meant. <br>
There can be a significant amount of non-verilog (not my choice) that sometime...
09:59 pm Verilog-mode Using AUTOs: Pragmas to disable Indentation for regions of code
I enjoy my verilog-mode indenting, and running from the command-line on a batch of files, but it obviously wasn't mea...
09:23 pm Verilog-mode Using - Non-AUTOS: RE: Indentation goes haywire when using xor (^)
In your code...

10/06/2011

07:31 pm Verilog-mode Using AUTOs: Inject endcomments after a block (e.g. endfunction, endtask, endmodule, `endif)
Is there a way to inject endcomments in a file (or region)?
- Brian

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