Verilator Documentation¶

Program Documentation¶

Tutorials¶

High Performance SoC Modeling with Verilator - A Tutorial for Cycle Accurate SystemC Model Creation and Optimization using Verilator. By Jeremy Bennett of Embecosm. Includes tips on optimizing performance and removing compile warnings.

Benchmarks¶

Verilog Simulator Benchmarks

Papers¶

Verilator: Fast, Free, but for Me? [pdf] - Presentation on open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. Presented by Wilson Snyder <wsnyder@wsnyder.org> to 2010 DVClub Bristol.

Verilator SystemC Environment Slides [pdf] - A paper on using Verilator inside a SystemC environment presented by Wilson Snyder <wsnyder@wsnyder.org> to the 2004 North American SystemC User's Group part of the Design Automation Conference.

Verilator Internals Slides [pdf] - A presentation on history, usage, and some internals of Verilator presented by Wilson Snyder <wsnyder@wsnyder.org> to Philips Semiconductors in July 2005.

Other References¶

Verilator's Wikipedia entry

Developing Silicon IP with Open Source Tools - Paper on economies of using Verilator and CovVise by Arthur Low.

vmodel - Tool to simulate Verilated Verilog modules inside MATLAB simulations