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This page contains documentation extracted from verilog-mode, revision 2014-10-03-c075a49-vpo. Functions are described here beginning with verilog-mode and verilog-auto, then alphabetically.

See also the other Verilog-mode Documentation

You may copy this document, but it will soon get out of date; you are thus better linking to &BASE;verilog-mode-help.html, or getting these pages from the Emacs help system.

Copyright 2006, the Free Software Foundation. By Michael McNamara (mac@verilog.com). and Wilson Snyder (wsnyder@wsnyder.org)


verilog-mode (function)

Verilog


verilog-auto (function)

Expand AUTO statements. Look for any /*AUTO...*/ commands in the code, as used in instantiations or argument headers. Update the list of signals following the /*AUTO...*/ command.

Use M-x verilog-delete-auto to remove the AUTOs.

Use M-x verilog-diff-auto to see differences in AUTO expansion.

Use M-x verilog-inject-auto to insert AUTOs for the first time.

Use M-x verilog-faq for a pointer to frequently asked questions.

For new users, we recommend setting verilog-case-fold to nil and verilog-auto-arg-sort to t.

The hooks verilog-before-auto-hook and verilog-auto-hook are called before and after this function, respectively.

For example:

	module ModuleName (/*AUTOARG*/);
	/*AUTOINPUT*/
	/*AUTOOUTPUT*/
	/*AUTOWIRE*/
	/*AUTOREG*/
	InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using:

	emacs --batch  <filenames.v>  -f verilog-batch-auto
Or fix indentation with:
	emacs --batch  <filenames.v>  -f verilog-batch-indent
Likewise, you can delete or inject AUTOs with:
	emacs --batch  <filenames.v>  -f verilog-batch-delete-auto
	emacs --batch  <filenames.v>  -f verilog-batch-inject-auto
Or check if AUTOs have the same expansion
	emacs --batch  <filenames.v>  -f verilog-batch-diff-auto

Using M-x describe-function, see also:

    verilog-auto-arg          for AUTOARG module instantiations
    verilog-auto-ascii-enum   for AUTOASCIIENUM enumeration decoding
    verilog-auto-assign-modport for AUTOASSIGNMODPORT assignment to/from modport
    verilog-auto-inout        for AUTOINOUT making hierarchy inouts
    verilog-auto-inout-comp   for AUTOINOUTCOMP copy complemented i/o
    verilog-auto-inout-in     for AUTOINOUTIN inputs for all i/o
    verilog-auto-inout-modport  for AUTOINOUTMODPORT i/o from an interface modport
    verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
    verilog-auto-inout-param  for AUTOINOUTPARAM copying params from elsewhere
    verilog-auto-input        for AUTOINPUT making hierarchy inputs
    verilog-auto-insert-lisp  for AUTOINSERTLISP insert code from lisp function
    verilog-auto-insert-last  for AUTOINSERTLAST insert code from lisp function
    verilog-auto-inst         for AUTOINST instantiation pins
    verilog-auto-star         for AUTOINST .* SystemVerilog pins
    verilog-auto-inst-param   for AUTOINSTPARAM instantiation params
    verilog-auto-logic        for AUTOLOGIC declaring logic signals
    verilog-auto-output       for AUTOOUTPUT making hierarchy outputs
    verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
    verilog-auto-reg          for AUTOREG registers
    verilog-auto-reg-input    for AUTOREGINPUT instantiation registers
    verilog-auto-reset        for AUTORESET flop resets
    verilog-auto-sense        for AUTOSENSE or AS always sensitivity lists
    verilog-auto-tieoff       for AUTOTIEOFF output tieoffs
    verilog-auto-undef        for AUTOUNDEF `undef of local `defines
    verilog-auto-unused       for AUTOUNUSED unused inputs/inouts
    verilog-auto-wire         for AUTOWIRE instantiation wires

verilog-read-defines for reading `define values verilog-read-includes for reading `includes

If you have bugs with these autos, please file an issue at URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR Wilson Snyder (wsnyder@wsnyder.org).


verilog-active-low-regexp (customizable variable)

If true, treat signals matching this regexp as active low. This is used for AUTORESET and AUTOTIEOFF. For proper behavior, you will probably also need verilog-auto-reset-widths set.


verilog-auto-arg (function)

Expand AUTOARG statements. Replace the argument declarations at the beginning of the module with ones automatically derived from input and output statements. This can be dangerous if the module is instantiated using position-based connections, so use only name-based when instantiating the resulting module. Long lines are split based on the `fill-column', see M-x set-fill-column.

Limitations:

Concatenation and outputting partial buses is not supported.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

For example:

	module ExampArg (/*AUTOARG*/);
	  input i;
	  output o;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampArg (/*AUTOARG*/
	  // Outputs
	  o,
	  // Inputs
	  i
	);
	  input i;
	  output o;
	endmodule

The argument declarations may be printed in declaration order to best suit order based instantiations, or alphabetically, based on the verilog-auto-arg-sort variable.

Formatting is controlled with verilog-auto-arg-format variable.

Any ports declared between the ( and /*AUTOARG*/ are presumed to be predeclared and are not redeclared by AUTOARG. AUTOARG will make a conservative guess on adding a comma for the first signal, if you have any ifdefs or complicated expressions before the AUTOARG you will need to choose the comma yourself.

Avoid declaring ports manually, as it makes code harder to maintain.


verilog-auto-arg-format (customizable variable)

Formatting to use for AUTOARG signal names. If 'packed', then as many inputs and outputs that fit within `fill-column' will be put onto one line.

If 'single', then a single input or output will be put onto each line.


verilog-auto-arg-sort (customizable variable)

Non-nil means AUTOARG signal names will be sorted, not in declaration order. Declaration order is advantageous with order based instantiations and is the default for backward compatibility. Sorted order reduces changes when declarations are moved around in a file, and it's bad practice to rely on order based instantiations anyhow.

See also verilog-auto-inst-sort.


verilog-auto-ascii-enum (function)

Expand AUTOASCIIENUM statements, as part of M-x verilog-auto. Create a register to contain the ASCII decode of an enumerated signal type. This will allow trace viewers to show the ASCII name of states.

First, parameters are built into an enumeration using the synopsys enum comment. The comment must be between the keyword and the symbol. (Annoying, but that's what Synopsys's dc_shell FSM reader requires.)

Next, registers which that enum applies to are also tagged with the same enum.

Finally, an AUTOASCIIENUM command is used.

The first parameter is the name of the signal to be decoded.

The second parameter is the name to store the ASCII code into. For the signal foo, I suggest the name _foo__ascii, where the leading _ indicates a signal that is just for simulation, and the magic characters _ascii tell viewers like Dinotrace to display in ASCII format.

The third optional parameter is a string which will be removed from the state names. It defaults to "" which removes nothing.

The fourth optional parameter is "onehot" to force one-hot decoding. If unspecified, if and only if the first parameter width is 2^(number of states in enum) and does NOT match the width of the enum, the signal is assumed to be a one-hot decode. Otherwise, it's a normal encoded state vector.

verilog-auto-wire-type may be used to change the datatype of the declarations.

"auto enum" may be used in place of "synopsys enum".

An example:

	//== State enumeration
	parameter [2:0] // synopsys enum state_info
			   SM_IDLE =  3'b000,
			   SM_SEND =  3'b001,
			   SM_WAIT1 = 3'b010;
	//== State variables
	reg [2:0]  /* synopsys enum state_info */
		   state_r;  /* synopsys state_vector state_r */
	reg [2:0]  /* synopsys enum state_info */
		   state_e1;

/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/

Typing M-x verilog-auto will make this into:

	... same front matter ...

/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/ // Beginning of automatic ASCII enum decoding reg [39:0] state_ascii_r; // Decode of state_r always @(state_r) begin case ({state_r}) SM_IDLE: state_ascii_r = "idle "; SM_SEND: state_ascii_r = "send "; SM_WAIT1: state_ascii_r = "wait1"; default: state_ascii_r = "%Erro"; endcase end // End of automatics


verilog-auto-assign-modport (function)

Expand AUTOASSIGNMODPORT statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified interface and modport and use to build assignments into the modport, for making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in that interface.

The third parameter is the instance name to use to dot reference into.

The optional fourth parameter is a regular expression, and only signals matching the regular expression will be included.

Limitations:

Interface names must be resolvable to filenames. See verilog-auto-inst.

Inouts are not supported, as assignments must be unidirectional.

If a signal is part of the interface header and in both a modport and the interface itself, it will not be listed. (As this would result in a syntax error when the connections are made.)

See the example in verilog-auto-inout-modport.


verilog-auto-hook (customizable variable)

Hook run after verilog-mode updates AUTOs.


verilog-auto-inout (function)

Expand AUTOINOUT statements, as part of M-x verilog-auto. Make inout statements for any inout signal in an /*AUTOINST*/ that isn't declared elsewhere inside the module.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-inout-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampInout (ov,i);
	   input i;
	   /*AUTOINOUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInout (ov,i);
	   input i;
	   /*AUTOINOUT*/
	   // Beginning of automatic inouts (from unused autoinst inouts)
	   inout [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Inouts
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inouts starting with i:

	   /*AUTOINOUT("^i")*/

verilog-auto-inout-comp (function)

Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert the inverse into the current module (inputs become outputs and vice-versa.) This is useful for making test and stimulus modules which need to have complementing I/O with another module. Any I/O which are already defined in this module will not be redefined. For the complement of this function, see verilog-auto-inout-module.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.

An example:

	module ExampShell (/*AUTOARG*/);
	   /*AUTOINOUTCOMP("ExampMain")*/
	endmodule

module ExampMain (i,o,io); input i; output o; inout io; endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io);
	   /*AUTOINOUTCOMP("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output i;
           inout io;
           input o;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTCOMP("ExampMain","^i")*/

verilog-auto-inout-ignore-regexp (customizable variable)

If non-nil, when creating AUTOINOUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.


verilog-auto-inout-in (function)

Expand AUTOINOUTIN statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert them as all inputs into the current module. This is useful for making monitor modules which need to see all signals as inputs based on another module. Any I/O which are already defined in this module will not be redefined. See also verilog-auto-inout-module.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.

An example:

	module ExampShell (/*AUTOARG*/);
	   /*AUTOINOUTIN("ExampMain")*/
	endmodule

module ExampMain (i,o,io); input i; output o; inout io; endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io);
	   /*AUTOINOUTIN("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           input i;
           input io;
           input o;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTCOMP("ExampMain","^i")*/

verilog-auto-inout-modport (function)

Expand AUTOINOUTMODPORT statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified interface and modport and insert into the current module. This is useful for making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in that interface.

The optional third parameter is a regular expression, and only signals matching the regular expression will be included.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Interface names must be resolvable to filenames. See verilog-auto-inst.

As with other autos, any inputs/outputs declared in the module will suppress the AUTO from redeclaring an inputs/outputs by the same name.

An example:

	interface ExampIf
	  ( input logic clk );
	   logic        req_val;
	   logic [7:0]  req_dat;
	   clocking mon_clkblk @(posedge clk);
	      input     req_val;
	      input     req_dat;
	   endclocking
	   modport mp(clocking mon_clkblk);
	endinterface

module ExampMain ( input clk, /*AUTOINOUTMODPORT("ExampIf" "mp")*/ // Beginning of automatic in/out/inouts (from modport) input [7:0] req_dat, input req_val // End of automatics ); /*AUTOASSIGNMODPORT("ExampIf" "mp")*/ endmodule

Typing M-x verilog-auto will make this into:

	...
	module ExampMain
	( input clk,
	  /*AUTOINOUTMODPORT("ExampIf" "mp")*/
	  // Beginning of automatic in/out/inouts (from modport)
	  input			req_dat,
	  input			req_val
	  // End of automatics
	);

If the modport is part of a UVM monitor/driver class, this creates a wrapper module that may be used to instantiate the driver/monitor using AUTOINST in the testbench.


verilog-auto-inout-module (function)

Expand AUTOINOUTMODULE statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert into the current module. This is useful for making null templates and shell modules which need to have identical I/O with another module. Any I/O which are already defined in this module will not be redefined. For the complement of this function, see verilog-auto-inout-comp, and to make monitors with all inputs, see verilog-auto-inout-in.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.

Signals declared as "output reg" or "output wire" etc will lose the wire/reg declaration so that shell modules may generate those outputs differently. However, "output logic" is propagated.

An example:

	module ExampShell (/*AUTOARG*/);
	   /*AUTOINOUTMODULE("ExampMain")*/
	endmodule

module ExampMain (i,o,io); input i; output o; inout io; endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io);
	   /*AUTOINOUTMODULE("ExampMain")*/
           // Beginning of automatic in/out/inouts (from specific module)
           output o;
           inout io;
           input i;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTMODULE("ExampMain","^i")*/

You may also provide an optional second regular expression, in which case only signals which have that pin direction and data type will be included. This matches against everything before the signal name in the declaration, for example against "input" (single bit), "output logic" (direction and type) or "output [1:0]" (direction and implicit type). You also probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o" against the previous example's module:

	   /*AUTOINOUTMODULE("ExampMain","","^output.*")*/

verilog-auto-inout-param (function)

Expand AUTOINOUTPARAM statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified module and insert into the current module. This is useful for making null templates and shell modules which need to have identical I/O with another module. Any I/O which are already defined in this module will not be redefined. For the complement of this function, see verilog-auto-inout-comp, and to make monitors with all inputs, see verilog-auto-inout-in.

Limitations:

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

Module names must be resolvable to filenames. See verilog-auto-inst.

Parameters are inserted in the same order as in the original module.

Parameters do not have values, which is SystemVerilog 2009 syntax.

An example:

	module ExampShell ();
	   /*AUTOINOUTPARAM("ExampMain")*/
	endmodule

module ExampMain (); parameter PARAM = 22; endmodule

Typing M-x verilog-auto will make this into:

	module ExampShell (/*AUTOARG*/i,o,io);
	   /*AUTOINOUTPARAM("ExampMain")*/
           // Beginning of automatic parameters (from specific module)
           parameter PARAM;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only parameters matching the regular expression will be included. For example the same expansion will result from only extracting parameters starting with i:

	   /*AUTOINOUTPARAM("ExampMain","^i")*/

verilog-auto-input (function)

Expand AUTOINPUT statements, as part of M-x verilog-auto. Make input statements for any input signal into an /*AUTOINST*/ that isn't declared elsewhere inside the module. This is useful for modules which only instantiate other modules.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-input-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampInput (ov,i);
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInput (ov,i);
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   // Beginning of automatic inputs (from unused autoinst inputs)
	   input	i;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting inputs starting with i:

	   /*AUTOINPUT("^i")*/

verilog-auto-input-ignore-regexp (customizable variable)

If non-nil, when creating AUTOINPUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.


verilog-auto-insert-last (function)

Expand AUTOINSERTLAST statements, as part of M-x verilog-auto. The Lisp code provided is called after all other AUTOS have been expanded, and the Lisp code generally will call `insert` to insert text into the current file beginning on the line after the AUTOINSERTLAST.

Other than when called (after AUTOs are expanded), the functionality is otherwise identical to AUTOINSERTLISP and verilog-auto-insert-lisp which executes before (as opposed to after) other AUTOs.

See verilog-auto-insert-lisp for examples.


verilog-auto-insert-lisp (function)

Expand AUTOINSERTLISP statements, as part of M-x verilog-auto. The Lisp code provided is called before other AUTOS are expanded, and the Lisp code generally will call `insert` to insert text into the current file beginning on the line after the AUTOINSERTLISP.

See also AUTOINSERTLAST and verilog-auto-insert-last which executes after (as opposed to before) other AUTOs.

See also AUTO_LISP, which takes a Lisp expression and evaluates it during verilog-auto-inst but does not insert any text.

An example:

	module ExampInsertLisp;
	   /*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
	endmodule

// For this example we declare the function in the // module's file itself. Often you'd define it instead // in a site-start.el or init file. /* Local Variables: eval: (defun my-verilog-insert-hello (who) (insert (concat "initial $write(\"hello " who "\");\n"))) End: */

Typing M-x verilog-auto will call my-verilog-insert-hello and expand the above into:

	// Beginning of automatic insert lisp
	initial $write("hello world");
	// End of automatics

You can also call an external program and insert the returned text:

	/*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
	// Beginning of automatic insert lisp
	//hello
	// End of automatics

verilog-auto-inst (function)

Expand AUTOINST statements, as part of M-x verilog-auto. Replace the pin connections to an instantiation or interface declaration with ones automatically derived from the module or interface header of the instantiated item.

If verilog-auto-star-expand is set, also expand SystemVerilog .* ports, and delete them before saving unless verilog-auto-star-save is set. See verilog-auto-star for more information.

The pins are printed in declaration order or alphabetically, based on the verilog-auto-inst-sort variable.

Limitations:

Module names must be resolvable to filenames by adding a verilog-library-extensions, and being found in the same directory, or by changing the variable verilog-library-flags or verilog-library-directories. Macros `modname are translated through the vh-{name} Emacs variable, if that is not found, it just ignores the `.

In templates you must have one signal per line, ending in a ), or ));, and have proper () nesting, including a final ); to end the template.

Typedefs must match verilog-typedef-regexp, which is disabled by default.

SystemVerilog multidimensional input/output has only experimental support.

SystemVerilog .name syntax is used if verilog-auto-inst-dot-name is set.

Parameters referenced by the instantiation will remain symbolic, unless verilog-auto-inst-param-value is set.

Gate primitives (and/or) may have AUTOINST for the purpose of AUTOWIRE declarations, etc. Gates are the only case when position based connections are passed.

The array part of arrayed instances are ignored; this may result in undesirable default AUTOINST connections; use a template instead.

For example, first take the submodule InstModule.v:

	module InstModule (o,i);
	   output [31:0] o;
	   input i;
	   wire [31:0] o = {32{i}};
	endmodule

This is then used in an upper level module:

	module ExampInst (o,i);
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInst (o,i);
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

Unless you are instantiating a module multiple times, or the module is something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY. It just makes for unmaintainable code. To sanitize signal names, try vrename from URL `http://www.veripool.org'.

When you need to violate this suggestion there are two ways to list exceptions, placing them before the AUTOINST, or using templates.

Any ports defined before the /*AUTOINST*/ are not included in the list of automatics. This is similar to making a template as described below, but is restricted to simple connections just like you normally make. Also note that any signals before the AUTOINST will only be picked up by AUTOWIRE if you have the appropriate // Input or // Output comment, and exactly the same line formatting as AUTOINST itself uses.

	InstModule instName
          (// Inputs
	   .i		(my_i_dont_mess_with_it),
	   /*AUTOINST*/
	   // Outputs
	   .ov		(ov[31:0]));

Templates:

For multiple instantiations based upon a single template, create a commented out template:

	/* InstModule AUTO_TEMPLATE (
		.sig3	(sigz[]),
		);
	*/

Templates go ABOVE the instantiation(s). When an instantiation is expanded verilog-mode simply searches up for the closest template. Thus you can have multiple templates for the same module, just alternate between the template for an instantiation and the instantiation itself. (For backward compatibility if no template is found above, it will also look below, but do not use this behavior in new designs.)

The module name must be the same as the name of the module in the instantiation name, and the code "AUTO_TEMPLATE" must be in these exact words and capitalized. Only signals that must be different for each instantiation need to be listed.

Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal.

Inside a template, a [][] in a connection name will behave similarly to a [] for scalar or single-dimensional connection; for a multidimensional connection it will print a comment similar to that printed when a template is not used. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.

Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.

If you have a complicated template, set verilog-auto-inst-template-numbers to see which regexps are matching. Don't leave that mode set after debugging is completed though, it will result in lots of extra differences and merge conflicts.

Setting verilog-auto-template-warn-unused will report errors if any template lines are unused.

For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .NotInTemplate	(NotInTemplate),
	    .ptl_bus		(ptl_busnew[3:0]),  // Templated
	    ....

Multiple Module Templates:

The same template lines can be applied to multiple modules with the syntax as follows:

	/* InstModuleA AUTO_TEMPLATE
	   InstModuleB AUTO_TEMPLATE
	   InstModuleC AUTO_TEMPLATE
	   InstModuleD AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/

Note there is only one AUTO_TEMPLATE opening parenthesis.

@ Templates:

It is common to instantiate a cell multiple times, so templates make it trivial to substitute part of the cell name into the connection name.

	/* InstName AUTO_TEMPLATE <optional "REGEXP"> (
		.sig1	(sigx[@]),
		.sig2	(sigy[@"(% (+ 1 @) 4)"]),
		);
	*/

If no regular expression is provided immediately after the AUTO_TEMPLATE keyword, then the @ character in any connection names will be replaced with the instantiation number; the first digits found in the cell's instantiation name.

If a regular expression is provided, the @ character will be replaced with the first () grouping that matches against the cell name. Using a regexp of "\([0-9]+\)" provides identical values for @ as when no regexp is provided. If you use multiple layers of parenthesis, "test\([^0-9]+\)_\([0-9]+\)" would replace @ with non-number characters after test and before _, whereas "\(test\([a-z]+\)_\([0-9]+\)\)" would replace @ with the entire match.

For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_mapvalidx		(ptl_mapvalid[@]),
		.ptl_mapvalidp1x	(ptl_mapvalid[@"(% (+ 1 @) 4)"]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(ptl_mapvalid[2]),
	    .ptl_mapvalidp1x		(ptl_mapvalid[3]));

Note the @ character was replaced with the 2 from "ms2m".

Alternatively, using a regular expression for @:

	/* InstModule AUTO_TEMPLATE "_\([a-z]+\)" (
		.ptl_mapvalidx		(@_ptl_mapvalid),
		.ptl_mapvalidp1x	(ptl_mapvalid_@),
		);
	*/
	InstModule ms2_FOO (/*AUTOINST*/);
	InstModule ms2_BAR (/*AUTOINST*/);

Typing M-x verilog-auto will make this into:

	InstModule ms2_FOO (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(FOO_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_FOO));
	InstModule ms2_BAR (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(BAR_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_BAR));

Regexp Templates:

A template entry of the form

	    .pci_req\([0-9]+\)_l	(pci_req_jtag_[\1]),

will apply an Emacs style regular expression search for any port beginning in pci_req followed by numbers and ending in _l and connecting that to the pci_req_jtag_[] net, with the bus subscript coming from what matches inside the first set of \( \). Thus pci_req2_l becomes pci_req_jtag_[2].

Since \([0-9]+\) is so common and ugly to read, a @ in the port name does the same thing. (Note a @ in the connection/replacement text is completely different -- still use \1 there!) Thus this is the same as the above template:

	    .pci_req@_l		(pci_req_jtag_[\1]),

Here's another example to remove the _l, useful when naming conventions specify _ alone to mean active low. Note the use of [] to keep the bus subscript:

	    .\(.*\)_l		(\1_[]),

Lisp Templates:

First any regular expression template is expanded.

If the syntax @"( ... )" is found in a connection, the expression in quotes will be evaluated as a Lisp expression, with @ replaced by the instantiation number. The MAPVALIDP1X example above would put @+1 modulo 4 into the brackets. Quote all double-quotes inside the expression with a leading backslash (\"...\"); or if the Lisp template is also a regexp template backslash the backslash quote (\\"...\\").

There are special variables defined that are useful in these Lisp functions:

	vl-name        Name portion of the input/output port.
	vl-bits        Bus bits portion of the input/output port ('[2:0]').
	vl-mbits       Multidimensional array bits for port ('[2:0][3:0]').
	vl-width       Width of the input/output port ('3' for [2:0]).
                       May be a (...) expression if bits isn't a constant.
	vl-dir         Direction of the pin input/output/inout/interface.
	vl-modport     The modport, if an interface with a modport.
	vl-cell-type   Module name/type of the cell ('InstModule').
	vl-cell-name   Instance name of the cell ('instName').

Normal Lisp variables may be used in expressions. See verilog-read-defines which can set vh-{definename} variables for use here. Also, any comments of the form:

	/*AUTO_LISP(setq foo 1)*/

will evaluate any Lisp expression inside the parenthesis between the beginning of the buffer and the point of the AUTOINST. This allows functions to be defined or variables to be changed between instantiations. (See also verilog-auto-insert-lisp if you want the output from your lisp function to be inserted.)

Note that when using lisp expressions errors may occur when @ is not a number; you may need to use the standard Emacs Lisp functions `number-to-string' and `string-to-number'.

After the evaluation is completed, @ substitution and [] substitution occur.

For more information see the M-x verilog-faq and forums at URL `http://www.veripool.org'.


verilog-auto-inst-dot-name (customizable variable)

Non-nil means when creating ports with AUTOINST, use .name syntax. This will use ".port" instead of ".port(port)" when possible. This is only legal in SystemVerilog files, and will confuse older simulators. Setting verilog-auto-inst-vector to nil may also be desirable to increase how often .name will be used.


verilog-auto-inst-param (function)

Expand AUTOINSTPARAM statements, as part of M-x verilog-auto. Replace the parameter connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.

See M-x verilog-auto-inst for limitations, and templates to customize the output.

For example, first take the submodule InstModule.v:

	module InstModule (o,i);
	   parameter PAR;
	endmodule

This is then used in an upper level module:

	module ExampInst (o,i);
	   parameter PAR;
	   InstModule #(/*AUTOINSTPARAM*/)
		instName (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampInst (o,i);
	   output o;
	   input i;
	   InstModule #(/*AUTOINSTPARAM*/
		        // Parameters
		        .PAR	(PAR));
		instName (/*AUTOINST*/);
	endmodule

Where the list of parameter connections come from the inst module.

Templates:

You can customize the parameter connections using AUTO_TEMPLATEs, just as you would with M-x verilog-auto-inst.

verilog-auto-inst-param-value (customizable variable)

Non-nil means AUTOINST will replace parameters with the parameter value. If nil, leave parameters as symbolic names.

Parameters must be in Verilog 2001 format #(...), and if a parameter is not listed as such there (as when the default value is acceptable), it will not be replaced, and will remain symbolic.

For example, imagine a submodule uses parameters to declare the size of its inputs. This is then used by an upper module:

	module InstModule (o,i);
	   parameter WIDTH;
	   input [WIDTH-1:0] i;
	endmodule

module ExampInst; InstModule #(.PARAM(10)) instName (/*AUTOINST*/ .i (i[PARAM-1:0]));

Note even though PARAM=10, the AUTOINST has left the parameter as a symbolic name. If verilog-auto-inst-param-value is set, this will instead expand to:

	module ExampInst;
	   InstModule
	     #(.PARAM(10))
	    instName
	     (/*AUTOINST*/
	      .i 	(i[9:0]));

verilog-auto-inst-sort (customizable variable)

Non-nil means AUTOINST signals will be sorted, not in declaration order. Also affects AUTOINSTPARAM. Declaration order is the default for backward compatibility, and as some teams prefer signals that are declared together to remain together. Sorted order reduces changes when declarations are moved around in a file.

See also verilog-auto-arg-sort.


verilog-auto-inst-template-numbers (customizable variable)

If true, when creating templated ports with AUTOINST, add a comment.

If t, the comment will add the line number of the template that was used for that port declaration. This setting is suggested only for debugging use, as regular use may cause a large numbers of merge conflicts.

If 'lhs', the comment will show the left hand side of the AUTO_TEMPLATE rule that is matched. This is less precise than numbering (t) when multiple rules have the same pin name, but won't merge conflict.


verilog-auto-inst-vector (customizable variable)

Non-nil means when creating default ports with AUTOINST, use bus subscripts. If nil, skip the subscript when it matches the entire bus as declared in the module (AUTOWIRE signals always are subscripted, you must manually declare the wire to have the subscripts removed.) Setting this to nil may speed up some simulators, but is less general and harder to read, so avoid.


verilog-auto-logic (function)

Expand AUTOLOGIC statements, as part of M-x verilog-auto. Make wire statements using the SystemVerilog logic keyword. This is currently equivalent to:

    /*AUTOWIRE*/

with the below at the bottom of the file

    // Local Variables:
    // verilog-auto-logic-type:"logic"
    // End:

In the future AUTOLOGIC may declare additional identifiers, while AUTOWIRE will not.


verilog-auto-output (function)

Expand AUTOOUTPUT statements, as part of M-x verilog-auto. Make output statements for any output signal from an /*AUTOINST*/ that isn't an input to another AUTOINST. This is useful for modules which only instantiate other modules.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

Typedefs must match verilog-typedef-regexp, which is disabled by default.

Signals matching verilog-auto-output-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

	module ExampOutput (ov,i);
	   input i;
	   /*AUTOOUTPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampOutput (ov,i);
	   input i;
	   /*AUTOOUTPUT*/
	   // Beginning of automatic outputs (from unused autoinst outputs)
	   output [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:

	   /*AUTOOUTPUT("^ov")*/

verilog-auto-output-every (function)

Expand AUTOOUTPUTEVERY statements, as part of M-x verilog-auto. Make output statements for any signals that aren't primary inputs or outputs already. This makes every signal in the design an output. This is useful to get Synopsys to preserve every signal in the design, since it won't optimize away the outputs.

An example:

	module ExampOutputEvery (o,i,tempa,tempb);
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampOutputEvery (o,i,tempa,tempb);
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   // Beginning of automatic outputs (every signal)
	   output	tempb;
	   output	tempa;
	   // End of automatics
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:

	   /*AUTOOUTPUTEVERY("^ov")*/

verilog-auto-output-ignore-regexp (customizable variable)

If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.


verilog-auto-reg (function)

Expand AUTOREG statements, as part of M-x verilog-auto. Make reg statements for any output that isn't already declared, and isn't a wire output from a block. verilog-auto-wire-type may be used to change the datatype of the declarations.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

This does NOT work on memories, declare those yourself.

An example:

	module ExampReg (o,i);
	   output o;
	   input i;
	   /*AUTOREG*/
	   always o = i;
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampReg (o,i);
	   output o;
	   input i;
	   /*AUTOREG*/
	   // Beginning of automatic regs (for this module's undeclared outputs)
	   reg		o;
	   // End of automatics
	   always o = i;
	endmodule

verilog-auto-reg-input (function)

Expand AUTOREGINPUT statements, as part of M-x verilog-auto. Make reg statements instantiation inputs that aren't already declared. This is useful for making a top level shell for testing the module that is to be instantiated.

Limitations:

This ONLY detects inputs of AUTOINSTants (see verilog-read-sub-decls).

This does NOT work on memories, declare those yourself.

An example (see verilog-auto-inst for what else is going on here):

	module ExampRegInput (o,i);
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampRegInput (o,i);
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
	   // Beginning of automatic reg inputs (for undeclared ...
	   reg [31:0]		iv;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
             (/*AUTOINST*/
	      // Outputs
	      .o		(o[31:0]),
	      // Inputs
	      .iv		(iv));
	endmodule

verilog-auto-reset (function)

Expand AUTORESET statements, as part of M-x verilog-auto. Replace the /*AUTORESET*/ comment with code to initialize all registers set elsewhere in the always block.

Limitations:

AUTORESET will not clear memories.

AUTORESET uses <= if the signal has a <= assignment in the block, else it uses =.

If <= is used, all = assigned variables are ignored if verilog-auto-reset-blocking-in-non is nil; they are presumed to be temporaries.

/*AUTORESET*/ presumes that any signals mentioned between the previous begin/case/if statement and the AUTORESET comment are being reset manually and should not be automatically reset. This includes omitting any signals used on the right hand side of assignments.

By default, AUTORESET will include the width of the signal in the autos, SystemVerilog designs may want to change this. To control this behavior, see verilog-auto-reset-widths. In some cases AUTORESET must use a '0 assignment and it will print NOWIDTH; use verilog-auto-reset-widths unbased to prevent this.

AUTORESET ties signals to deasserted, which is presumed to be zero. Signals that match verilog-active-low-regexp will be deasserted by tying them to a one.

AUTORESET may try to reset arrays or structures that cannot be reset by a simple assignment, resulting in compile errors. This is a feature to be taken as a hint that you need to reset these signals manually (or put them into a "`ifdef NEVER signal<=`0; `endif" so Verilog-Mode ignores them.)

An example:

    always @(posedge clk or negedge reset_l) begin
        if (!reset_l) begin
            c <= 1;
            /*AUTORESET*/
        end
        else begin
            a <= in_a;
            b <= in_b;
            c <= in_c;
        end
    end

Typing M-x verilog-auto will make this into:

    always @(posedge core_clk or negedge reset_l) begin
        if (!reset_l) begin
            c <= 1;
            /*AUTORESET*/
            // Beginning of autoreset for uninitialized flops
            a <= 0;
            b = 0;   // if verilog-auto-reset-blocking-in-non true
            // End of automatics
        end
        else begin
            a <= in_a;
            b  = in_b;
            c <= in_c;
        end
    end

verilog-auto-reset-blocking-in-non (customizable variable)

Non-nil means AUTORESET will reset blocking statements. When true, AUTORESET will reset in blocking statements those signals which were assigned with blocking assignments (=) even in a block with non-blocking assignments (<=).

If nil, all blocking assigned signals are ignored when any non-blocking assignment is in the AUTORESET block. This allows blocking assignments to be used for temporary values and not have those temporaries reset. See example in verilog-auto-reset.


verilog-auto-reset-widths (customizable variable)

True means AUTORESET should determine the width of signals. This is then used to set the width of the zero (32'h0 for example). This is required by some lint tools that aren't smart enough to ignore widths of the constant zero. This may result in ugly code when parameters determine the MSB or LSB of a signal inside an AUTORESET.

If nil, AUTORESET uses "0" as the constant.

If 'unbased', AUTORESET used the unbased unsized literal "'0" as the constant. This setting is strongly recommended for SystemVerilog designs.


verilog-auto-sense (function)

Expand AUTOSENSE statements, as part of M-x verilog-auto. Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short) with one automatically derived from all inputs declared in the always statement. Signals that are generated within the same always block are NOT placed into the sensitivity list (see verilog-auto-sense-include-inputs). Long lines are split based on the `fill-column', see M-x set-fill-column.

Limitations:

Verilog does not allow memories (multidimensional arrays) in sensitivity lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.

Constant signals:

AUTOSENSE cannot always determine if a `define is a constant or a signal (it could be in an include file for example). If a `define or other signal is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT declaration anywhere in the module (parenthesis are required):

	/* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */

Better yet, use a parameter, which will be understood to be constant automatically.

OOps!

If AUTOSENSE makes a mistake, please report it. (First try putting a begin/end after your always!) As a workaround, if a signal that shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above. If a signal should be in the sensitivity list wasn't, placing it before the /*AUTOSENSE*/ comment will prevent it from being deleted when the autos are updated (or added if it occurs there already).

An example:

	   always @ (/*AS*/) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Typing M-x verilog-auto will make this into:

	   always @ (/*AS*/ina or inb) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Note in Verilog 2001, you can often get the same result from the new @* operator. (This was added to the language in part due to AUTOSENSE!)

	   always @* begin
	      outin = ina | inb | `constant;
	      out = outin;
	   end

verilog-auto-sense-include-inputs (customizable variable)

Non-nil means AUTOSENSE should include all inputs. If nil, only inputs that are NOT output signals in the same block are included.


verilog-auto-star (function)

Expand SystemVerilog .* pins, as part of M-x verilog-auto.

If verilog-auto-star-expand is set, .* pins are treated if they were AUTOINST statements, otherwise they are ignored. For safety, Verilog mode will also ignore any .* that are not last in your pin list (this prevents it from deleting pins following the .* when it expands the AUTOINST.)

On writing your file, unless verilog-auto-star-save is set, any non-templated expanded pins will be removed. You may do this at any time with M-x verilog-delete-auto-star-implicit.

If you are converting a module to use .* for the first time, you may wish to use M-x verilog-inject-auto and then replace the created AUTOINST with .*.

See verilog-auto-inst for examples, templates, and more information.


verilog-auto-star-expand (customizable variable)

Non-nil means to expand SystemVerilog .* instance ports. They will be expanded in the same way as if there was an AUTOINST in the instantiation. See also verilog-auto-star and verilog-auto-star-save.


verilog-auto-star-save (customizable variable)

Non-nil means save to disk SystemVerilog .* instance expansions. A nil value indicates direct connections will be removed before saving. Only meaningful to those created due to verilog-auto-star-expand being set.

Instead of setting this, you may want to use /*AUTOINST*/, which will always be saved.


verilog-auto-template-warn-unused (customizable variable)

Non-nil means report warning if an AUTO_TEMPLATE line is not used. This feature is not supported before Emacs 21.1 or XEmacs 21.4.


verilog-auto-tieoff (function)

Expand AUTOTIEOFF statements, as part of M-x verilog-auto. Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output signals to deasserted.

/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all outputs in the module, and if that input is not otherwise declared as a register or wire, creates a tieoff.

AUTORESET ties signals to deasserted, which is presumed to be zero. Signals that match verilog-active-low-regexp will be deasserted by tying them to a one.

You can add signals you do not want included in AUTOTIEOFF with verilog-auto-tieoff-ignore-regexp.

verilog-auto-wire-type may be used to change the datatype of the declarations.

verilog-auto-reset-widths may be used to change how the tieoff value's width is generated.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTPARAM("Foo")*/
	/*AUTOINOUTMODULE("Foo")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

Typing M-x verilog-auto will make this into:

    module ExampStub (/*AUTOINST*/...);
	/*AUTOINOUTPARAM("Foo")*/
	/*AUTOINOUTMODULE("Foo")*/
        // Beginning of autotieoff
        output [2:0] foo;
        // End of automatics

/*AUTOTIEOFF*/ // Beginning of autotieoff wire [2:0] foo = 3'b0; // End of automatics ... endmodule


verilog-auto-tieoff-ignore-regexp (customizable variable)

If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.


verilog-auto-undef (function)

Expand AUTOUNDEF statements, as part of M-x verilog-auto. Take any `defines since the last AUTOUNDEF in the current file and create `undefs for them. This is used to insure that file-local defines do not pollute the global `define name space.

Limitations:

AUTOUNDEF presumes any identifier following `define is the name of a define. Any `ifdefs are ignored.

AUTOUNDEF suppresses creating an `undef for any define that was `undefed before the AUTOUNDEF. This may be used to work around the ignoring of `ifdefs as shown below.

An example:

	`define XX_FOO
	`define M_BAR(x)
	`define M_BAZ
	...
	`ifdef NEVER
	  `undef M_BAZ	// Emacs will see this and not `undef M_BAZ
	`endif
	...
	/*AUTOUNDEF*/

Typing M-x verilog-auto will make this into:

	...
	/*AUTOUNDEF*/
	// Beginning of automatic undefs
	`undef XX_FOO
	`undef M_BAR
	// End of automatics

You may also provide an optional regular expression, in which case only defines the regular expression will be undefed.


verilog-auto-unused (function)

Expand AUTOUNUSED statements, as part of M-x verilog-auto. Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused input and inout signals.

/*AUTOUNUSED*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all inputs and inouts in the module, and if that input is not otherwise used, adds it to a comma separated list.

The comma separated list is intended to be used to create a _unused_ok signal. Using the exact name "_unused_ok" for name of the temporary signal is recommended as it will insure maximum forward compatibility, it also makes lint warnings easy to understand; ignore any unused warnings with "unused" in the signal name.

To reduce simulation time, the _unused_ok signal should be forced to a constant to prevent wiggling. The easiest thing to do is use a reduction-and with 1'b0 as shown.

This way all unused signals are in one place, making it convenient to add your tool's specific pragmas around the assignment to disable any unused warnings.

You can add signals you do not want included in AUTOUNUSED with verilog-auto-unused-ignore-regexp.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTPARAM("Examp")*/
	/*AUTOINOUTMODULE("Examp")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

Typing M-x verilog-auto will make this into:

        ...
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
			    // Beginning of automatics
			    unused_input_a,
			    unused_input_b,
			    unused_input_c,
			    // End of automatics
                            1'b0};
        // verilator lint_on  UNUSED
    endmodule

verilog-auto-unused-ignore-regexp (customizable variable)

If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.


verilog-auto-wire (function)

Expand AUTOWIRE statements, as part of M-x verilog-auto. Make wire statements for instantiations outputs that aren't already declared. verilog-auto-wire-type may be used to change the datatype of the declarations.

Limitations:

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls), and all buses must have widths, such as those from AUTOINST, or using [] in AUTO_TEMPLATEs.

This does NOT work on memories or SystemVerilog .name connections, declare those yourself.

Verilog mode will add "Couldn't Merge" comments to signals it cannot determine how to bus together. This occurs when you have ports with non-numeric or non-sequential bus subscripts. If Verilog mode mis-guessed, you'll have to declare them yourself.

An example (see verilog-auto-inst for what else is going on here):

	module ExampWire (o,i);
	   output o;
	   input i;
	   /*AUTOWIRE*/
           InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing M-x verilog-auto will make this into:

	module ExampWire (o,i);
	   output o;
	   input i;
	   /*AUTOWIRE*/
	   // Beginning of automatic wires
	   wire [31:0]		ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	   wire o = | ov;
	endmodule

verilog-auto-wire-type (customizable variable)

Non-nil specifies the data type to use with verilog-auto-wire etc. Set this to "logic" for SystemVerilog code, or use verilog-auto-logic.


verilog-batch-diff-auto (function)

For use with --batch, perform automatic differences as a stand-alone tool. This sets up the appropriate Verilog mode environment, expand automatics with M-x verilog-diff-auto on all command-line files, and reports an error if any differences are observed. This is appropriate for adding to regressions to insure automatics are always properly maintained.


verilog-before-auto-hook (customizable variable)

Hook run before verilog-mode updates AUTOs.


verilog-before-delete-auto-hook (customizable variable)

Hook run before verilog-mode deletes AUTOs.


verilog-case-fold (customizable variable)

Non-nil means verilog-mode regexps should ignore case. This variable is t for backward compatibility; nil is suggested.


verilog-delete-auto (function)

Delete the automatic outputs, regs, and wires created by M-x verilog-auto. Use M-x verilog-auto to re-insert the updated AUTOs.

The hooks verilog-before-delete-auto-hook and verilog-delete-auto-hook are called before and after this function, respectively.


verilog-delete-auto-hook (customizable variable)

Hook run after verilog-mode deletes AUTOs.


verilog-delete-auto-star-implicit (function)

Delete all .* implicit connections created by verilog-auto-star. This function will be called automatically at save unless verilog-auto-star-save is set, any non-templated expanded pins will be removed.


verilog-diff-auto (function)

Expand AUTOs in a temporary buffer and indicate any change. Whitespace is ignored when detecting differences, but once a difference is detected, whitespace differences may be shown.

To call this from the command line, see M-x verilog-batch-diff-auto.

The action on differences is selected with verilog-diff-function. The default is verilog-diff-report which will report an error and run `ediff' in interactive mode, or `diff' in batch mode.


verilog-diff-function (variable)

Function to run when verilog-diff-auto detects differences. Function takes three arguments, the original buffer, the difference buffer, and the point in original buffer with the first difference.


verilog-diff-report (function)

Report differences detected with verilog-diff-auto. Differences are between buffers B1 and B2, starting at point DIFFPT. This function is called via verilog-diff-function.


verilog-faq (function)

Tell the user their current version, and where to get the FAQ etc.


verilog-inject-auto (function)

Examine legacy non-AUTO code and insert AUTOs in appropriate places.

Any always @ blocks with sensitivity lists that match computed lists will be replaced with /*AS*/ comments.

Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with have identical names will be deleted.

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to support adding new ports. You may wish to delete older ports yourself.

For example:

	module ExampInject (i, o);
	  input i;
	  input j;
	  output o;
	  always @ (i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     j(j));
	endmodule

Typing M-x verilog-inject-auto will make this into:

	module ExampInject (i, o/*AUTOARG*/
	  // Inputs
	  j);
	  input i;
	  output o;
	  always @ (/*AS*/i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     /*AUTOINST*/
	     // Outputs
	     j(j));
	endmodule

verilog-library-directories (customizable variable)

List of directories when looking for files for /*AUTOINST*/. The directory may be relative to the current file, or absolute. Environment variables are also expanded in the directory names. Having at least the current directory is a good idea.

You might want these defined in each file; put at the *END* of your file something like:

    // Local Variables:
    // verilog-library-directories:("." "subdir" "subdir2")
    // End:

Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.

See also verilog-library-flags, verilog-library-files and verilog-library-extensions.


verilog-library-extensions (customizable variable)

List of extensions to use when looking for files for /*AUTOINST*/. See also verilog-library-flags, verilog-library-directories.


verilog-library-files (customizable variable)

List of files to search for modules. AUTOINST will use this when it needs to resolve a module name. This is a complete path, usually to a technology file with many standard cells defined in it.

You might want these defined in each file; put at the *END* of your file something like:

    // Local Variables:
    // verilog-library-files:("/some/path/technology.v" "/some/path/tech2.v")
    // End:

Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.

See also verilog-library-flags, verilog-library-directories.


verilog-library-flags (customizable variable)

List of standard Verilog arguments to use for /*AUTOINST*/. These arguments are used to find files for verilog-auto, and match the flags accepted by a standard Verilog-XL simulator.

    -f filename     Reads more verilog-library-flags from the filename.
    +incdir+dir     Adds the directory to verilog-library-directories.
    -Idir           Adds the directory to verilog-library-directories.
    -y dir          Adds the directory to verilog-library-directories.
    +libext+.v      Adds the extensions to verilog-library-extensions.
    -v filename     Adds the filename to verilog-library-files.

filename Adds the filename to verilog-library-files. This is not recommended, -v is a better choice.

You might want these defined in each file; put at the *END* of your file something like:

    // Local Variables:
    // verilog-library-flags:("-y dir -y otherdir")
    // End:

Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.

See also the variables mentioned above.


verilog-read-defines (function)

Read `defines and parameters for the current file, or optional FILENAME. If the filename is provided, verilog-library-flags will be used to resolve it. If optional RECURSE is non-nil, recurse through `includes.

Parameters must be simple assignments to constants, or have their own "parameter" label rather than a list of parameters. Thus:

    parameter X = 5, Y = 10;	// Ok
    parameter X = {1'b1, 2'h2};	// Ok
    parameter X = {1'b1, 2'h2}, Y = 10;	// Bad, make into 2 parameter lines

Defines must be simple text substitutions, one on a line, starting at the beginning of the line. Any ifdefs or multiline comments around the define are ignored.

Defines are stored inside Emacs variables using the name vh-{definename}.

This function is useful for setting vh-* variables. The file variables feature can be used to set defines that verilog-mode can see; put at the *END* of your file something like:

    // Local Variables:
    // vh-macro:"macro_definition"
    // End:

If macros are defined earlier in the same file and you want their values, you can read them automatically (provided `enable-local-eval' is on):

    // Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-defines "group_standard_includes.v")
    // End:

Note these are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!

If you want to disable the "Process `eval' or hook local variables" warning message, you need to add to your init file:

    (setq enable-local-eval t)

verilog-read-includes (function)

Read `includes for the current file. This will find all of the `includes which are at the beginning of lines, ignoring any ifdefs or multiline comments around them. verilog-read-defines is then performed on the current and each included file.

It is often useful put at the *END* of your file something like:

    // Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-includes)
    // End:

Note includes are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!

It is good to get in the habit of including all needed files in each .v file that needs it, rather than waiting for compile time. This will aid this process, Verilint, and readability. To prevent defining the same variable over and over when many modules are compiled together, put a test around the inside each include file:

foo.v (an include file):

	`ifdef _FOO_V	// include if not already included
	`else
	`define _FOO_V
	... contents of file
	`endif // _FOO_V

verilog-read-sub-decls (function)

Internally parse signals going to modules under this module. Return an array of [ outputs inouts inputs ] signals for modules that are instantiated in this module. For example if declare A A (.B(SIG)) and SIG is an output, then SIG will be included in the list.

This only works on instantiations created with /*AUTOINST*/ converted by M-x verilog-auto-inst. Otherwise, it would have to read in the whole component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and // Outputs comments above subcell signals, for example:

	module ModuleName (
	    // Outputs
	    .out (out),
	    // Inputs
	    .in  (in));

verilog-typedef-regexp (customizable variable)

If non-nil, regular expression that matches Verilog-2001 typedef names. For example, "_t$" matches typedefs named with _t, as in the C language. See also verilog-case-fold.