1
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------------------------------------------------------------
|
2
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making verilator in src
|
3
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/Library/Developer/CommandLineTools/usr/bin/make -C src
|
4
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/Library/Developer/CommandLineTools/usr/bin/make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial
|
5
|
make[2]: Nothing to be done for `serial'.
|
6
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/Library/Developer/CommandLineTools/usr/bin/make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj
|
7
|
Compile flags: g++ -I/usr/local/include -MMD -I. -I.. -I.. -I../../include -I../../include -DYYDEBUG -ggdb -DVL_DEBUG -D_GLIBCXX_DEBUG -MP -Qunused-arguments -faligned-new -Wno-unused-parameter -Wno-undefined-bool-conversion -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="/Users/echi/App/systemc/include" -DDEFENV_SYSTEMC_LIBDIR="/Users/echi/App/systemc/lib" -DDEFENV_VERILATOR_ROOT="/Users/echi/hobby/cpp/verilator"
|
8
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/Library/Developer/CommandLineTools/usr/bin/make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov
|
9
|
make[2]: Nothing to be done for `serial_vlcov'.
|
10
|
/Library/Developer/CommandLineTools/usr/bin/make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj
|
11
|
Compile flags: g++ -I/usr/local/include -MMD -I. -I.. -I.. -I../../include -I../../include -DYYDEBUG -ggdb -DVL_DEBUG -D_GLIBCXX_DEBUG -MP -Qunused-arguments -faligned-new -Wno-unused-parameter -Wno-undefined-bool-conversion -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="/Users/echi/App/systemc/include" -DDEFENV_SYSTEMC_LIBDIR="/Users/echi/App/systemc/lib" -DDEFENV_VERILATOR_ROOT="/Users/echi/hobby/cpp/verilator"
|
12
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/Library/Developer/CommandLineTools/usr/bin/make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial
|
13
|
make[2]: Nothing to be done for `serial'.
|
14
|
/Library/Developer/CommandLineTools/usr/bin/make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj
|
15
|
Compile flags: g++ -I/usr/local/include -MMD -I. -I.. -I.. -I../../include -I../../include -DYYDEBUG -O2 -MP -Qunused-arguments -faligned-new -Wno-unused-parameter -Wno-undefined-bool-conversion -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="/Users/echi/App/systemc/include" -DDEFENV_SYSTEMC_LIBDIR="/Users/echi/App/systemc/lib" -DDEFENV_VERILATOR_ROOT="/Users/echi/hobby/cpp/verilator"
|
16
|
test_regress/t/t_a_first_cc.pl
|
17
|
======================================================================
|
18
|
dist/t_a_first_cc: ==================================================
|
19
|
-Skip: dist/t_a_first_cc: scenario 'dist' not enabled for test
|
20
|
dist/t_a_first_cc: %Skip: Skip: scenario 'dist' not enabled for test
|
21
|
test_regress/t/t_a_first_sc.pl
|
22
|
======================================================================
|
23
|
dist/t_a_first_sc: ==================================================
|
24
|
-Skip: dist/t_a_first_sc: scenario 'dist' not enabled for test
|
25
|
dist/t_a_first_sc: %Skip: Skip: scenario 'dist' not enabled for test
|
26
|
for p in examples/* ; do \
|
27
|
/Library/Developer/CommandLineTools/usr/bin/make -C $p VERILATOR_ROOT=`pwd` || exit 10; \
|
28
|
done
|
29
|
-- Verilator hello-world simple example
|
30
|
-- VERILATE ----------------
|
31
|
/Users/echi/hobby/cpp/verilator/bin/verilator -cc --exe top.v sim_main.cpp
|
32
|
-- COMPILE -----------------
|
33
|
/Library/Developer/CommandLineTools/usr/bin/make -j 4 -C obj_dir -f Vtop.mk
|
34
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -c -o sim_main.o ../sim_main.cpp
|
35
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -c -o verilated.o /Users/echi/hobby/cpp/verilator/include/verilated.cpp
|
36
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop.cpp > Vtop__ALLcls.cpp
|
37
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop__Syms.cpp > Vtop__ALLsup.cpp
|
38
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -c -o Vtop__ALLsup.o Vtop__ALLsup.cpp
|
39
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
|
40
|
Archiving Vtop__ALL.a ...
|
41
|
ar r Vtop__ALL.a Vtop__ALLcls.o Vtop__ALLsup.o
|
42
|
ar: creating archive Vtop__ALL.a
|
43
|
ranlib Vtop__ALL.a
|
44
|
g++ sim_main.o verilated.o Vtop__ALL.a -o Vtop -lm -lstdc++
|
45
|
-- RUN ---------------------
|
46
|
obj_dir/Vtop
|
47
|
Hello World!
|
48
|
- top.v:10: Verilog $finish
|
49
|
-- DONE --------------------
|
50
|
Note: Once this example is understood, see examples/tracing_c.
|
51
|
Note: Also see the EXAMPLE section in the verilator manpage/document.
|
52
|
-- Verilator hello-world simple example
|
53
|
-- VERILATE ----------------
|
54
|
/Users/echi/hobby/cpp/verilator/bin/verilator -sc --exe top.v sc_main.cpp
|
55
|
-- COMPILE -----------------
|
56
|
/Library/Developer/CommandLineTools/usr/bin/make -j 4 -C obj_dir -f Vtop.mk
|
57
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=1 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -c -o sc_main.o ../sc_main.cpp
|
58
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=1 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -c -o verilated.o /Users/echi/hobby/cpp/verilator/include/verilated.cpp
|
59
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop.cpp > Vtop__ALLcls.cpp
|
60
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop__Syms.cpp > Vtop__ALLsup.cpp
|
61
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=1 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
|
62
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=1 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -c -o Vtop__ALLsup.o Vtop__ALLsup.cpp
|
63
|
Archiving Vtop__ALL.a ...
|
64
|
ar r Vtop__ALL.a Vtop__ALLcls.o Vtop__ALLsup.o
|
65
|
ar: creating archive Vtop__ALL.a
|
66
|
ranlib Vtop__ALL.a
|
67
|
g++ -L/Users/echi/App/systemc/lib sc_main.o verilated.o Vtop__ALL.a -o Vtop -lm -lstdc++ -lsystemc
|
68
|
-- RUN ---------------------
|
69
|
obj_dir/Vtop
|
70
|
Hello World!
|
71
|
- top.v:10: Verilog $finish
|
72
|
-- DONE --------------------
|
73
|
Note: Once this example is understood, see examples/tracing_sc.
|
74
|
Note: Also see the EXAMPLE section in the verilator manpage/document.
|
75
|
|
76
|
-- Verilator tracing example
|
77
|
|
78
|
-- VERILATE ----------------
|
79
|
/Users/echi/hobby/cpp/verilator/bin/verilator -cc --exe -O2 -x-assign 0 -Wall --trace --assert --coverage -f input.vc top.v sim_main.cpp
|
80
|
|
81
|
-- COMPILE -----------------
|
82
|
/Library/Developer/CommandLineTools/usr/bin/make -j 4 -C obj_dir -f ../Makefile_obj
|
83
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -O2 -fstrict-aliasing -c -o sim_main.o ../sim_main.cpp
|
84
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -O2 -fstrict-aliasing -c -o verilated.o /Users/echi/hobby/cpp/verilator/include/verilated.cpp
|
85
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -O2 -fstrict-aliasing -c -o verilated_cov.o /Users/echi/hobby/cpp/verilator/include/verilated_cov.cpp
|
86
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -O2 -fstrict-aliasing -c -o verilated_vcd_c.o /Users/echi/hobby/cpp/verilator/include/verilated_vcd_c.cpp
|
87
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop.cpp > Vtop__ALLcls.cpp
|
88
|
/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop__Trace.cpp Vtop__Syms.cpp Vtop__Trace__Slow.cpp > Vtop__ALLsup.cpp
|
89
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -O2 -fstrict-aliasing -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
|
90
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -MMD -MP -DVL_DEBUG=1 -c -o Vtop__ALLsup.o Vtop__ALLsup.cpp
|
91
|
Archiving Vtop__ALL.a ...
|
92
|
ar r Vtop__ALL.a Vtop__ALLcls.o Vtop__ALLsup.o
|
93
|
ar: creating archive Vtop__ALL.a
|
94
|
ranlib Vtop__ALL.a
|
95
|
g++ sim_main.o verilated.o verilated_cov.o verilated_vcd_c.o Vtop__ALL.a -o Vtop -lm -lstdc++
|
96
|
|
97
|
-- RUN ---------------------
|
98
|
obj_dir/Vtop +trace
|
99
|
Enabling waves into logs/vlt_dump.vcd...
|
100
|
[1] Model running...
|
101
|
|
102
|
[1] clk=0 rstl=1 iquad=1246 -> oquad=1247 owide=3_22222222_11111112
|
103
|
[2] clk=0 rstl=0 iquad=1258 -> oquad=0 owide=0_00000000_00000000
|
104
|
[3] clk=1 rstl=0 iquad=126a -> oquad=0 owide=0_00000000_00000000
|
105
|
[4] clk=1 rstl=0 iquad=127c -> oquad=0 owide=0_00000000_00000000
|
106
|
[5] clk=1 rstl=0 iquad=128e -> oquad=0 owide=0_00000000_00000000
|
107
|
[6] clk=1 rstl=0 iquad=12a0 -> oquad=0 owide=0_00000000_00000000
|
108
|
[7] clk=1 rstl=0 iquad=12b2 -> oquad=0 owide=0_00000000_00000000
|
109
|
[8] clk=0 rstl=0 iquad=12c4 -> oquad=0 owide=0_00000000_00000000
|
110
|
[9] clk=0 rstl=0 iquad=12d6 -> oquad=0 owide=0_00000000_00000000
|
111
|
[10] clk=0 rstl=1 iquad=12e8 -> oquad=12e9 owide=3_22222222_11111112
|
112
|
[11] clk=0 rstl=1 iquad=12fa -> oquad=12fb owide=3_22222222_11111112
|
113
|
[12] clk=0 rstl=1 iquad=130c -> oquad=130d owide=3_22222222_11111112
|
114
|
[13] clk=1 rstl=1 iquad=131e -> oquad=131f owide=3_22222222_11111112
|
115
|
[14] clk=1 rstl=1 iquad=1330 -> oquad=1331 owide=3_22222222_11111112
|
116
|
[15] clk=1 rstl=1 iquad=1342 -> oquad=1343 owide=3_22222222_11111112
|
117
|
[16] clk=1 rstl=1 iquad=1354 -> oquad=1355 owide=3_22222222_11111112
|
118
|
[17] clk=1 rstl=1 iquad=1366 -> oquad=1367 owide=3_22222222_11111112
|
119
|
[18] clk=0 rstl=1 iquad=1378 -> oquad=1379 owide=3_22222222_11111112
|
120
|
[19] clk=0 rstl=1 iquad=138a -> oquad=138b owide=3_22222222_11111112
|
121
|
[20] clk=0 rstl=1 iquad=139c -> oquad=139d owide=3_22222222_11111112
|
122
|
[21] clk=0 rstl=1 iquad=13ae -> oquad=13af owide=3_22222222_11111112
|
123
|
[22] clk=0 rstl=1 iquad=13c0 -> oquad=13c1 owide=3_22222222_11111112
|
124
|
[23] clk=1 rstl=1 iquad=13d2 -> oquad=13d3 owide=3_22222222_11111112
|
125
|
[24] clk=1 rstl=1 iquad=13e4 -> oquad=13e5 owide=3_22222222_11111112
|
126
|
[25] clk=1 rstl=1 iquad=13f6 -> oquad=13f7 owide=3_22222222_11111112
|
127
|
[26] clk=1 rstl=1 iquad=1408 -> oquad=1409 owide=3_22222222_11111112
|
128
|
[27] clk=1 rstl=1 iquad=141a -> oquad=141b owide=3_22222222_11111112
|
129
|
[28] clk=0 rstl=1 iquad=142c -> oquad=142d owide=3_22222222_11111112
|
130
|
[29] clk=0 rstl=1 iquad=143e -> oquad=143f owide=3_22222222_11111112
|
131
|
[30] clk=0 rstl=1 iquad=1450 -> oquad=1451 owide=3_22222222_11111112
|
132
|
[31] clk=0 rstl=1 iquad=1462 -> oquad=1463 owide=3_22222222_11111112
|
133
|
[32] clk=0 rstl=1 iquad=1474 -> oquad=1475 owide=3_22222222_11111112
|
134
|
[33] clk=1 rstl=1 iquad=1486 -> oquad=1487 owide=3_22222222_11111112
|
135
|
[34] clk=1 rstl=1 iquad=1498 -> oquad=1499 owide=3_22222222_11111112
|
136
|
[35] clk=1 rstl=1 iquad=14aa -> oquad=14ab owide=3_22222222_11111112
|
137
|
[36] clk=1 rstl=1 iquad=14bc -> oquad=14bd owide=3_22222222_11111112
|
138
|
[37] clk=1 rstl=1 iquad=14ce -> oquad=14cf owide=3_22222222_11111112
|
139
|
[38] clk=0 rstl=1 iquad=14e0 -> oquad=14e1 owide=3_22222222_11111112
|
140
|
[39] clk=0 rstl=1 iquad=14f2 -> oquad=14f3 owide=3_22222222_11111112
|
141
|
[40] clk=0 rstl=1 iquad=1504 -> oquad=1505 owide=3_22222222_11111112
|
142
|
[41] clk=0 rstl=1 iquad=1516 -> oquad=1517 owide=3_22222222_11111112
|
143
|
[42] clk=0 rstl=1 iquad=1528 -> oquad=1529 owide=3_22222222_11111112
|
144
|
[43] fastclk is 5 times faster than clk
|
145
|
|
146
|
*-* All Finished *-*
|
147
|
- sub.v:45: Verilog $finish
|
148
|
[43] clk=1 rstl=1 iquad=153a -> oquad=153b owide=3_22222222_11111112
|
149
|
|
150
|
-- COVERAGE ----------------
|
151
|
/Users/echi/hobby/cpp/verilator/bin/verilator_coverage --annotate logs/annotated logs/coverage.dat
|
152
|
Total coverage (8/20) 40.00%
|
153
|
See lines with '%00' in logs/annotated
|
154
|
|
155
|
-- DONE --------------------
|
156
|
To see waveforms, open vlt_dump.vcd in a waveform viewer
|
157
|
|
158
|
|
159
|
-- Verilator tracing example
|
160
|
|
161
|
-- VERILATE ----------------
|
162
|
/Users/echi/hobby/cpp/verilator/bin/verilator -sc --exe -O2 -x-assign 0 -Wall --trace --assert --coverage -f input.vc top.v sc_main.cpp
|
163
|
|
164
|
-- COMPILE ----------------=
|
165
|
/Library/Developer/CommandLineTools/usr/bin/make -j 4 -C obj_dir -f ../Makefile_obj
|
166
|
g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o sc_main.o ../sc_main.cpp
|
167
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o verilated.o /Users/echi/hobby/cpp/verilator/include/verilated.cpp
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o verilated_cov.o /Users/echi/hobby/cpp/verilator/include/verilated_cov.cpp
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o verilated_vcd_c.o /Users/echi/hobby/cpp/verilator/include/verilated_vcd_c.cpp
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o verilated_vcd_sc.o /Users/echi/hobby/cpp/verilator/include/verilated_vcd_sc.cpp
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/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop.cpp > Vtop__ALLcls.cpp
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/usr/bin/perl /Users/echi/hobby/cpp/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop__Trace.cpp Vtop__Syms.cpp Vtop__Trace__Slow.cpp > Vtop__ALLsup.cpp
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -O2 -fstrict-aliasing -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
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g++ -I. -MMD -I/Users/echi/hobby/cpp/verilator/include -I/Users/echi/hobby/cpp/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=1 -DVM_SC=1 -DVM_TRACE=1 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I/Users/echi/App/systemc/include -MMD -MP -DVL_DEBUG=1 -Wno-deprecated -c -o Vtop__ALLsup.o Vtop__ALLsup.cpp
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Archiving Vtop__ALL.a ...
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ar r Vtop__ALL.a Vtop__ALLcls.o Vtop__ALLsup.o
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ar: creating archive Vtop__ALL.a
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ranlib Vtop__ALL.a
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g++ -L/Users/echi/App/systemc/lib sc_main.o verilated.o verilated_cov.o verilated_vcd_c.o verilated_vcd_sc.o Vtop__ALL.a -o Vtop -lm -lstdc++ -lsystemc
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-- RUN ---------------------
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obj_dir/Vtop +trace
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[0] Model running...
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Enabling waves into logs/vlt_dump.vcd...
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[43] fastclk is 5 times faster than clk
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*-* All Finished *-*
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- sub.v:45: Verilog $finish
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-- COVERAGE ----------------
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/Users/echi/hobby/cpp/verilator/bin/verilator_coverage --annotate logs/annotated logs/coverage.dat
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Total coverage (6/20) 30.00%
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See lines with '%00' in logs/annotated
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-- DONE --------------------
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To see waveforms, open vlt_dump.vcd in a waveform viewer
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/Library/Developer/CommandLineTools/usr/bin/make -C test_regress
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/usr/bin/perl driver.pl -j 0 --vlt --vltmt --dist
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driver.pl: Found 8 cores, using -j 9
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== Many jobs; redirecting STDIN
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======================================================================
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dist/t_EXAMPLE: ==================================================
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-Skip: dist/t_EXAMPLE: scenario 'dist' not enabled for test
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dist/t_EXAMPLE: %Skip: Skip: scenario 'dist' not enabled for test
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Tests passed!
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Now type 'make install' to install.
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Or type 'make' inside an examples subdirectory.
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