Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

build_and_run.sh

Junyi Xie, 04/12/2019 06:49 PM

Download (301 Bytes)

 
1
export VERILATOR_ROOT="replace with your verilator root"
2
${VERILATOR_ROOT}/bin/verilator -Wall --cc --trace --trace-structs interface_for_loop_tb.sv --exe InterfaceForLoopTest.cpp -FI sample_intf.sv
3
make -j -C obj_dir -f Vinterface_for_loop_tb.mk Vinterface_for_loop_tb
4
obj_dir/Vinterface_for_loop_tb