Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Vtopmod.xml

Kanad Kanhere, 05/16/2019 03:39 PM

Download (2.92 KB)

 
1
<?xml version="1.0" ?>
2
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
3
<verilator_xml>
4
  <files>
5
    <file id="a" filename="AstRoot" language="1800-2017"/>
6
    <file id="b" filename="COMMAND_LINE" language="1800-2017"/>
7
    <file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
8
    <file id="d" filename="src/topmod.sv" language="1800-2005"/>
9
  </files>
10
  <module_files>
11
    <file id="d" filename="src/topmod.sv" language="1800-2005"/>
12
  </module_files>
13
  <cells>
14
    <cell fl="d1" name="topmod" submodname="topmod" hier="topmod"/>
15
  </cells>
16
  <netlist>
17
    <module fl="d1" name="topmod" origName="topmod" topModule="1">
18
      <var fl="d2" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
19
      <var fl="d3" name="res_n" dtype_id="1" dir="input" vartype="logic" origName="res_n"/>
20
      <var fl="d4" name="d" dtype_id="1" dir="input" vartype="logic" origName="d"/>
21
      <var fl="d5" name="q" dtype_id="1" dir="output" vartype="logic" origName="q"/>
22
      <task fl="d8" name="error">
23
        <var fl="d8" name="msg" dtype_id="2" dir="input" vartype="string" origName="msg"/>
24
        <display fl="d9" displaytype="$write">
25
          <sformatf fl="d9" name="[%0t] %%Error: topmod.sv:9: Assertion failed in %m: ERROR: %@\n" dtype_id="2">
26
            <time fl="d9" dtype_id="3"/>
27
            <varref fl="d9" name="msg" dtype_id="2"/>
28
            <scopename fl="d9" dtype_id="3"/>
29
          </sformatf>
30
        </display>
31
        <stop fl="d9"/>
32
      </task>
33
      <always fl="d12">
34
        <sentree fl="d12">
35
          <senitem fl="d12" edgeType="POS">
36
            <varref fl="d12" name="clk" dtype_id="1"/>
37
          </senitem>
38
        </sentree>
39
        <begin fl="d13">
40
          <if fl="d14">
41
            <varref fl="d14" name="res_n" dtype_id="1"/>
42
            <begin fl="d15">
43
              <assigndly fl="d16" dtype_id="1">
44
                <const fl="d16" name="1'h0" dtype_id="1"/>
45
                <varref fl="d16" name="q" dtype_id="1"/>
46
              </assigndly>
47
              <if fl="d18">
48
                <varref fl="d18" name="d" dtype_id="1"/>
49
                <begin fl="d19">
50
                  <taskref fl="d20" name="error">
51
                    <arg fl="d20">
52
                      <const fl="d20" name="\"invalid input during reset\"" dtype_id="2"/>
53
                    </arg>
54
                  </taskref>
55
                </begin>
56
              </if>
57
            </begin>
58
            <begin fl="d25">
59
              <assigndly fl="d26" dtype_id="1">
60
                <varref fl="d26" name="d" dtype_id="1"/>
61
                <varref fl="d26" name="q" dtype_id="1"/>
62
              </assigndly>
63
            </begin>
64
          </if>
65
        </begin>
66
      </always>
67
    </module>
68
    <typetable fl="a0">
69
      <basicdtype  fl="d9" id="3" name="QData" left="63" right="0"/>
70
      <basicdtype  fl="d2" id="1" name="logic"/>
71
      <basicdtype  fl="d8" id="2" name="string"/>
72
    </typetable>
73
  </netlist>
74
</verilator_xml>