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0001-Do-not-overwrite-existing-assignments-in-new_contass.patch

Stefan Tauner, 03/18/2016 03:37 PM

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View differences:

Netlist/Module.pm
207 207
    # Create a new statement under this module
208 208
    if (!defined $params{name} || $params{name} eq '') {
209 209
	# Blank instance name; invent a new one; use the next instance number in this module t$
210
	$params{name} = '__unnamed_statement_' . ((scalar keys %{$self->_statements}) + 1);
210
	# However, if there were deletions this name is already occupied.
211
	# Try to find an unused one...
212
	my $i = scalar keys %{$self->_statements};
213
	my $tmp;
214
	do {
215
	    $i++;
216
	    $tmp = '__unnamed_statement_' . $i;
217
	} while (defined($self->_statements->{$tmp}));
218
	$params{name} = $tmp;
211 219
    }
212 220
    # Create a new object; pass the potentially modified options
213 221
    my $newref = new Verilog::Netlist::ContAssign(%params, module=>$self,);
214
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