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Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE?

Added by Ted Huang about 2 months ago

AUTOINST would create all ports and AUTOWIRE those ports in .v files. Is it possible to do them only for those which are listed in AUTO_TEMPLATE? Those unwanted ports would not be seen at top level. Or maybe a function like /*AUTO_EXCLUDE*/ can exclude those unwanted ports.
Example: 
module sub ( 
    input a,
    output b,
    output unused_c,
);
    assign b = ~a;
endmodule

module top (
    input test
);
/*AUTOWIRE*/
wire b;
/*sub AUTO_TEMPLATE (
    .a(test),
    .b(b));*/
sub u_sub (/*AUTOINST*/
    .a(test),
    .b(b)
);
endmodule

Replies (5)

RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE? - Added by Wilson Snyder about 2 months ago

Not directly, but you can get a similar effect that is perhaps sufficient with roughly

   /* abc AUTO_TEMPLATE
     (
      // Outputs
      .signal_c                         (signal_c),
      // Inputs
      .signal_b                         (signal_b[2:0]),
      .\(.*\)                           ({\1[]}),
    );
    */

   abc u_abc
     (/*AUTOINST*/
      // Outputs
      .signal_c                         (signal_c),              // Templated
      // Inputs
      .signal_a                         ({signal_a[1:0]}),       // Templated
      .signal_b                         (signal_b[2:0]));        // Templated

...
// Local Variables:
// verilog-auto-ignore-concat: t
// End:

RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE? - Added by Brian Magnuson 20 days ago

I have a similar need. I have some 3rd party IP (i.e. I can't easily change underlying Verilog) that exposes power/ground pins as defined in the corresponding .lib file. If certain tools even see these ports mentioned in the Verilog I get fatal errors.

It's a pretty niche use case to be sure and my workaround is seriously fragile as it relies on several implementation details of AUTOINST (e.g. those trailing line comments and comma are not optional), but it does seem to work.


`define DUMMY_CONNECT(x)

ip u_ip
    (`DUMMY_CONNECT(.VCC())
     `DUMMY_CONNECT(.VDD())//,
     `DUMMY_CONNECT(.VSSI())//,
     /*AUTOINST*/
     // Outputs
     .O1                               (O1),
     .O2                               (O2),
     // Inputs
     .I1                               (I1),
     .I2                               (I2),
     .I3                               (I3));

A more (ahem) robust solution would need a special annotation in AUTO_TEMPLATE as OP suggested or maybe something like verilog-auto-inst-port-ignore-regexp?

RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE? - Added by Wilson Snyder 14 days ago

Do you both think would it be better to have an only-insert-if-in-template option, or a exclude-this-port-regexp (e.g. listing VCC/VDD/VSSI) option?

RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE? - Added by Brian Magnuson 13 days ago

I think the only-insert-if-in-template is nicer since the regexp, as a file-wide option, would impact multiple templates.

You can always defeat the 'only' where needed with .\(.*\) (\1[]),

RE: Is it possible to AUTOINST/AUTOWIRE ports only for those which are listed in AUTO_TEMPLATE? - Added by Wilson Snyder 13 days ago

Added `verilog-auto-inst-template-required' to only insert AUTOINST ports inside an AUTO_TEMPLATE.

In git and version 2020-01-03-a15251f-mod-vpo.

    (1-5/5)