Project

General

Profile

[logo] 
 
Home
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

number of whitespaces between port name & signal name + indention + tabs replacement

Added by DIMA DMITRY 7 months ago

Hi there,

Is there a way to control number of spaces between the port name and the connected signal in the module instantiation and also align the connected signals?

E.g. I'd like having something like following (3 whitespaces between port name and signal):
.port_0<ws><ws><ws>(signal_0), 
.port_1<ws><ws><ws>(signal_1), 
.port_2<ws><ws><ws>(signal_2), 

where <ws> is whitespace

Is there a way to replace tabs with whitespaces? How to indent the signals in the module instantiation?

Thank you!


Replies (3)

RE: number of whitespaces between port name & signal name + indention + tabs replacement - Added by Wilson Snyder 7 months ago

Not currently, sorry. verilog-auto-inst-column lets you set the absolute column, but not relative column.

RE: number of whitespaces between port name & signal name + indention + tabs replacement - Added by DIMA DMITRY 7 months ago

Is there a way to replace tabs with whitespaces when AUTOs are triggered? Currently all the indention is done with tabs... How can I do the same with whitespaces?

RE: number of whitespaces between port name & signal name + indention + tabs replacement - Added by Wilson Snyder 7 months ago

Verilog-mode uses the standard Emacs settings to decide if indents with tabs, so "(setq indent-tabs-mode nil)"

Or if you want to untab even stuff the user inserted, add a hook that calls "(untabify)".

    (1-3/3)