Defining a Sorting order for AUTOINPUTS/AUTOOUTPUTS based on regex of verilog port names .
Hi Veripool team,
Question about defining a sorting order for AUTOINPUTS and OUTPUTS.
The current sorting order for AUTOINPUTS and OUTPUTS is - 1) Direction, numerical sorting of portwidths, lexicographical sorting of port name.
Is there a way a user can customize this sorting order. The motivation is cluster the signals that being to a a bus together. Here's an example - Assume that you several AXI buses which are named as - AxiBus1, AxiBus2, AxiBus3.
The individual signals of these buses get auto-sorted by default as - ARREADY_AxiBus1; ARREADY_AxiBus2; ARREADY_AxiBus3;
AWREADY_AxiBus1; AWREADY_AxiBus2; AWREADY_AxiBus3;
Instead it would be more meaningful to group them by buses as - ARREADY_AxiBus1; AWREADY_AxiBus1;
If you assume that the user has no flexibility to modify the names, is there a way to modify the sorting order using regex for verilog portnames.
RE: Defining a Sorting order for AUTOINPUTS/AUTOOUTPUTS based on regex of verilog port names . - Added by Wilson Snyder 12 days ago
AUTOINPUT and AUTOOUTPUT are separate commands, so each will and must do inputs and outputs separately. Then it sorts by name. Width is not part of the sort.
Anyhow, there's presently no option to change this. I'm reluctant to add one as there's so many variations it's unlikely to satisfy everyone. I would suggest that rather than fight it use one of the two common practices, either 1. put the container of the bus first in the signal name, or 2. use structs. Both are much cleaner to read generally. (Also note while we could fix the sort order for verilog-mode, most waveform tools would still resort them, so you're still better off putting buses lexicographical ajacent.)
AxiBus1_ARREADT; AxiBus1_AWREADT; AxiBus2_ARREADT; AxiBus2_AWREADT; AxiBus3_ARREADT; AxiBus3_AWREADT;