Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Reserved keywords

Added by Simon M over 1 year ago

Why are "soft" and "program" treated as reserved words in Verilog::Netlist ?


Replies (5)

RE: Reserved keywords - Added by Wilson Snyder over 1 year ago

They are SystemVerilog keywords. Use --language or `begin_keywords, or similar setting if you're stuck in Verilog 2001 land.

RE: Reserved keywords - Added by Simon M over 1 year ago

Thanks.

Now, the follow up. It looks like if I use Verilog::EditFiles to split one file into multiple files, and my input file has multiple `begin_keywords and `end_keywords, it picks up and includes the `begin_keywords in the output file, but the `end_keywords doesn't seem to make it into the output file.

RE: Reserved keywords - Added by Simon M over 1 year ago

Also, I see that "program" is a SystemVerilog keyword, but I see no indication that "soft" is a SystemVerilog keyword.

RE: Reserved keywords - Added by Wilson Snyder over 1 year ago

IEEE 1800-2012 Table 22-6.

RE: Reserved keywords - Added by Wilson Snyder over 1 year ago

Now, the follow up. It looks like if I use Verilog::EditFiles to split one file into multiple files, and my input file has multiple `begin_keywords and `end_keywords, it picks up and includes the `begin_keywords in the output file, but the `end_keywords doesn't seem to make it into the output file.

Hmm, yes makes sense that would be a bug as it doesn't know to put it on every file. You can file an issue here, perhaps you could also submit a patch to fix it?

    (1-5/5)