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verilog mode - utility to determine the hierarchy of a design,

Added by Moshe M 6 months ago

in the verilog-mode FAQ you are suggestion the following :

The filenames need to be provided in a bottom-up order. For a utility to determine the hierarchy of a design, see vhier in Verilog-Perl.

https://www.veripool.org/projects/verilog-mode/wiki/Faq#How-do-I-update-AUTOs-from-the-command-line

Do you have a simple Perl example code that parse the design hier and runs auto-connect on each file

Thanks!


Replies (1)

RE: verilog mode - utility to determine the hierarchy of a design, - Added by Wilson Snyder 6 months ago

I don't have an example. sorry. You should be able to use 'vhier --module-files' then reformat that output to make a new command to run emacs.

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