any chance of gettting deassign working?
This a description of deassign, which, in theory is synthesizable. It would help compile Xilinx libraries. http://www.asic-world.com/verilog/vbehave1.html
It seems it might be easy to do something with that.
Deassign isn't synthesizable, you're looking at a library cell that isn't synthesized. Furthermore it's pretty much never used even in behavioral code; Xilinx should have known better. BTW the usage of 'assign' in a non-continuous mode isn't supported either.
For now you need to write a more sanely modeled version of their memories etc and substitute it in. As long as it is a rewrite and no Xilinx IP is disclosed it would be good to contribute this back so the community could maintain it and have a good substitution story.
RE: any chance of gettting deassign working? - Added by Slava B 10 days ago
Any news related to the substitution story mentioned by Wilson? I cannot verilate a project due to usage of deassign in the vendor library.
RE: any chance of gettting deassign working? - Added by Wilson Snyder 10 days ago
There wasn't a suggested change to Verilator, the assumption is the user (you) will make a substitute module. Sorry.