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Support nested SytemVerilog interface as a port connection in a module
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#5066
opened Apr 25, 2024 by
sterin
Probable bug in force behavior
new
New issue not seen by maintainers
#5062
opened Apr 22, 2024 by
jackkoenig
Fusing macro argument easts up whitespace
area: parser
Issue involves SystemVerilog parsing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5061
opened Apr 21, 2024 by
tudortimi
Compile error when using module variable in class defined under module
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5060
opened Apr 21, 2024 by
tudortimi
Restore ability to hard-remove tracing
new
New issue not seen by maintainers
#5053
opened Apr 17, 2024 by
nickelpro
No warning/error if a signal is driven by both concurrent and continuous assignment
new
New issue not seen by maintainers
#5052
opened Apr 16, 2024 by
goekce
Internal Error: Variable inlining should make this impossible with v5.024
new
New issue not seen by maintainers
#5050
opened Apr 15, 2024 by
wltr
Add error when display a compound type
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5049
opened Apr 15, 2024 by
goekce
Wires driven through virtual interface traced improperly
area: tracing
Issue involves tracing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5044
opened Apr 10, 2024 by
RootCubed
Verilator not handling hierarchical signal references correctly
area: vpi/dpi/api
Issue involves VPI, DPI, or verilated.h interface API
status: discussion
Issue is waiting for discussions to resolve
#5041
opened Apr 9, 2024 by
slmnemo
Support generating SAIF file for power estimation
status: discussion
Issue is waiting for discussions to resolve
#5037
opened Apr 5, 2024 by
ayanbanrj
Verilator's vpiStringVal implementation masks byte values of 32 and 0
area: vpi/dpi/api
Issue involves VPI, DPI, or verilated.h interface API
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5036
opened Apr 4, 2024 by
mjeje
Fatal error: 'experimental/coroutine' file not found, on macOS using Clang latest
area: portability
Issue involves operating system/compiler portability
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5030
opened Mar 31, 2024 by
selimsandal
Being able to specify a zero width in an indexed part-select operation violates LRM
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5028
opened Mar 30, 2024 by
chykon
Class specialization is ignored for associative array as a class type parameter
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5022
opened Mar 27, 2024 by
esynr3z
Fix comparison of data types
status: asked reporter
Bug is waiting for reporter to answer a question
#5005
opened Mar 20, 2024 by
tastynoob
"Error-LIFETIME" when using a clocking block inside a submodule
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#5004
opened Mar 19, 2024 by
abarajithan11
Internal error on using constant variable within array assignment
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4998
opened Mar 18, 2024 by
esynr3z
NBA order graph of t_timing_nba is incorrect
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4993
opened Mar 16, 2024 by
gezalore
Declaring a constant with simultaneous initialization may result in an error depending on the lifetime and context
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4992
opened Mar 16, 2024 by
chykon
error: invalid types'WData {aka unsigned int}[unsigned int]"for array subscript
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4989
opened Mar 16, 2024 by
futurehome
Is selectable diagnostic message for $finish supported?
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4981
opened Mar 14, 2024 by
dominiksalvet
Fix evaluating final blocks on fatal
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4980
opened Mar 14, 2024 by
dominiksalvet
Linter allows commas in instance parameters where they are not allowed in Verilog
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4979
opened Mar 13, 2024 by
paul-demo
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