Project

General

Profile

[logo] 
 
Home
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Reduce Compile Memory

Added by Kevin Hurd about 4 years ago

Is there a way to reduce the required memory to compile a model; specifically the g++ compile?

I tried: verilator -O2 -Wall --inline-mult 400 --output-split 50000 ... make OPT_FAST="-O1 -fstrict-aliasing" -j 8 ...

However, the cc1plus (g++) process still needs >36GB of VM to compile?

I couldn't figure out how to try llvm.

Other than the huge compile footprint, I have found the tool to be awesome!


Replies (4)

RE: Reduce Compile Memory - Added by Kevin Hurd about 4 years ago

I manually flattened several of the highly replicated modules and that seems to have helped quite a bit!

RE: Reduce Compile Memory - Added by Ivan H almost 4 years ago

Can you give out a bit more detail on what you did in the end, and how it affected the compile time/memory? I am running into similar issues...

RE: Reduce Compile Memory - Added by Frederic Requin almost 4 years ago

I use :

verilator -cc -no-decoration -output-split 20000 -output-split-ctrace 10000 -O3 -CFLAGS -Wno-attributes -CFLAGS -O2 ...

make CXX=clang OBJCACHE=ccache VM_PARALLEL_BUILDS=1 -j -f ...

I works well on big design (100 KLUTs on an FPGA).

I ran into problems when trying to simulate post map or post route designs, I had to increase verilator stack size up to 8MB using : peflags -x0x800000 /usr/local/bin/verilator_bin.exe

RE: Reduce Compile Memory - Added by Kevin Hurd 10 months ago

Solved this by switching to clang, which ended up being 10x faster. GCC required creating a monster large file, which was the bottleneck.

    (1-4/4)