Can you force evaluation of a signal every tick
I have a PLL model that uses `system_c to create a C++ object that then uses the global main_time variable to synthesize a faster clock after figuring out the time delta of rising edges of the input clock. It has worked great for us in general for quite a while. I just ran into a problem with it on a new design, though. It seems if I cascade two PLL's, the second one does not get eval'd frequently enough and the higher clock rate does not get created correctly. It seems like a fan in logic optimization is causing it not to work. If I manually edit the generated C++, I can remove the if statement around the eval call to the PLL module and it starts working.
My question: is there some way to force eval of a variable on every tick so that eval is called even in the fan-in cone does not have any changes?
Not sure if this will do what you want, but something like this?
reg writeme /*verilator public_flat_rw @(posedge clk) */;
I don't think @* works, but we could teach it how to do that.
That seems to be working...