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Verilator extension for Ruby

Added by Shinobu TAKANASHI over 2 years ago

Hi all,

After 3 days struggling, I could managed to release the initial version of Verilator extention generator(call it VerilatorGen.rb) on github.

https://github.com/sin00b/VerilatorGen.rb

Though it's still far from sophisticated, neither tested enough, I guess it's runnable on Linux including RVM environment.

FYI, I didn't use VPI nor DPI. All the thing I did was to wrap those code under obj_dir/ by using SWIG. So hopefully the simulation speed would not be slower so much.

Also, I'm not yet familiar with Verilator, SWIG and even C++. :-) I just think it must be fun if I could write Verilog test bench in Ruby.

Not sure if there's wrappers for other languages, I guess you can refer my code. (swig template is here-documented)

So that's it! Feel free to comment, suggest or even complain. :-D

Thanks,

Shinobu TAKANASHI


Replies (12)

RE: Verilator extension for Ruby - Added by Wilson Snyder over 2 years ago

Thanks for the announcement. I don't use ruby myself but took a look at your repo and seems sensible. I have dreams of someday hooking the verilator XML output into SWIG to replace Verilog-Perl, but as it's not my present job role probably won't come to be.

Lisp Was: Verilator extension for Ruby - Added by Anthony Green over 2 years ago

Hi,

I wrote a similar tool last week called wrapilator, but it does Common Lisp, not Ruby.   See my github page for details and examples... https://github.com/atgreen/wrapilator

Anthony Green

RE: Verilator extension for Ruby - Added by Shareef Jalloq over 2 years ago

Thanks for this! I've only just started using Verilator and am having trouble getting my head round C++ which I've never used before. Your solution gives me just the one headache to solve first - the general testbench structure that works best.

Here's another Ruby example I set up.

module top (/*AUTOARG*/
   // Outputs
   full,
   // Inputs
   clk, reset_n
   );

   input clk;
   input reset_n;

   output full;

   reg [4:0] count_r /*verilator public*/;

   always@(posedge clk or negedge reset_n)
     if(!reset_n)
       count_r <= 5'd0;
     else
       if(!&count_r)
     count_r <= count_r + 1'b1;

   assign full = &count_r;

endmodule // top
#!/usr/bin/env ruby

require "./verilator" 

class Fixnum
  def to_hex(bits)
    rjust = (bits/4 + (bits.modulo(4)==0 ? 0 : 1))
    "0x" + self.to_s(16).rjust(rjust, "0")
  end
end

class TestBench

  attr_reader :top, :cyc

  def initialize(top)
    @top = top
    @cyc = 0
  end

  def tick
    @top.clk = 0
    @top.eval
    @top.clk = 1
    @top.eval
    @top.clk = 0
    @cyc+=1
  end

  def reset
    @top.reset_n = 1
    tick
    @top.reset_n = 0
    2.times { tick }
    @top.reset_n = 1
    tick
  end

  def finished
    @top.full == 1
  end

  def counter
    @top.top.count_r.to_hex(5)
  end
end

tb = TestBench.new(Verilator::Vtop.new)
tb.reset

while(!tb.finished) do
  tb.tick
  puts "cycle: #{tb.cyc} / counter: #{tb.counter} / tb.top.full: #{tb.top.full} " 
end

puts "Simulation ended successfully" 

RE: Verilator extension for Ruby - Added by Shinobu TAKANASHI over 2 years ago

@Wilson,

Thanks for your comment. I haven't use Verilog-Perl yet, but it's for static analysis of Verilog code? Also I guess SWIG does output XML from C/C++, but does not parse XML.

Anyway it must be interesting to make use of Verilator's XML output.

@Anthony,

I didn't expected Lisp wrapper! Yours looks cool.

@Shareef,

Happy to hear that you use this! I'm also a starter of Verilator and yeah, neither good at C++. That's exactly my motivation. I can suggest to use unit test frameworks such as Test::Unit or RSpec.

Thanks,

Shinobu

RE: Verilator extension for Ruby - Added by Wilson Snyder over 2 years ago

Verilog-Perl is a parser for simple "hacking" on Verilog programs/netlists. It doesn't fully understand the design like Verilator does.

If you haven't already you might want to read "Which Parser Package" under Verilog-Perl: WHICH PARSER PACKAGE?

RE: Verilator extension for Ruby - Added by Alexis G over 2 years ago

I am interested about what has been said here. Nevertheless, I don't see what we can do with the xml file generated by Verilator using --xml-only neither why it'd be useful.

RE: Verilator extension for Ruby - Added by Wilson Snyder over 2 years ago

--xml is used for people building parsers. This isn't related to ruby.

RE: Verilator extension for Ruby - Added by Alexis G over 2 years ago

For which purpose ? I don't see why using the xml file would be better to interface Verilator with another language or even with swig.

RE: Verilator extension for Ruby - Added by Wilson Snyder over 2 years ago

--xml isn't used for interfacing, it's used for writing parsers. See wikipedia etc for what a "abstract syntax tree" is used for.

RE: Verilator extension for Ruby - Added by Alexis G over 2 years ago

Sorry for my stupid question but I haven't found clear relation between your answer and his post.

Wilson Snyder wrote:

[...]I have dreams of someday hooking the verilator XML output into SWIG to replace Verilog-Perl[...]

I am not familiar with Verilator nor Swig yet but I'd like to understand what the intention behind what you said and why it'd be interesting to do so.

Moreover I thought Verilator and Verilog-perl were separated. It seems you're using Verilog-perl as a verilog parser for Verilator.

If I well understood, you'd like to use Verilator only to generate the AST, then use another language to effectively make the program, in that case the simulation will be done by the language and not C++ anymore. It'll be obviously slower and we'll need to maintain both. In a more general matter, you'd like to insert the AST into SWIG and SWIG will automatically generate the code. Am I right ?

RE: Verilator extension for Ruby - Added by Wilson Snyder over 2 years ago

Please first read up on what Verilog-Perl does. Verilog-Perl has a parser in it for writing tools, and is in no way a simulator. The idea would be to throw the Verilog-Perl parser away, and instead use the Verilator parser to replace it. This would be by having Verilog-Perl call verilator to make an XML output, then Verilog-Perl would take that XML output and map it to the parser callbacks. Or more generally, take the AST and have a SWIG language independent system so you could write tools that need the parse results in perl or python or whatever.

RE: Verilator extension for Ruby - Added by Alexis G over 2 years ago

I didn't see the point to have two different parsers generating two different AST. Why not having different C++ libraries instead of C++ code in Verilator and Perl libs doing the same thing? In that case Verilator could be only an app that calls libs. It seems functions are duplicated in C++ and Perl. Am I missing the relation with Perl language and HW dev ?

I understand it may be a stupid discussion for those who have developed and worked with Veripool's stuffs for a while but I am curious and try to figure out the current state.

TAKANASHI-san made a tool to call the Verilator's simulator from Ruby/Lisp/Python (other topics). SWIG is a tool to interface C/C++ with another language. Therefore I don't understand the relation between the Verilator's AST or even Verilog-perl with this. I don't see how the AST would be used in SWIG.

Anyway, I might not be enough documented or I might not have enough background to understand. It will be very handful if we can call Verilator from another language without using swig. I am just trying to find a way to contribute.

Thank you for your answers,

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