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verilator unpacked dimension signal dependency without circular logic error

Added by Christopher Russell over 2 years ago

After reviewing the similarity of my issue to the issue here: https://www.veripool.org/issues/739-Verilator-Multidimensional-arrays-and-UNOPTFLAT-warning#note-1

I would like to ask the complexity needed to modify verilator to treat unpacked dimensions of a single signal as separate signals for the purpose of circular logic detection. This becomes very useful for scalable algorithms in verilog where the current dimension has dependence on the result of the previous dimension.

I mainly concerned about this statement if I don't fix this issue: "(Unfortunately) There are other bugs about UNOPTFLAT here, for example bug63 on a version of this with bit numbers. In brief the cost is as much as dividing performance of your whole model by the number of loops; Verilator reevaluates ALL combinatorial code when a change occurs, and there may be a change for each loop."

Take the below code for example with a priority built in:
logic [NUM_FOO-2:0] select [NUM_FOO-1:0];
logic foo [NUM_FOO-1:0];
always_comb begin
  for(int i = 0; i < NUM_FOO; i++) begin
    foo[i] = { /* default logic goes here which could be complex */ };
    for(int previous = i-1; previous >= 0; previous--) begin
      if(select[i][previous]) begin
        foo[i] = foo[previous];
        break;
      end
    end
  end
end

I get a circular logic fail here although each unpacked dimension doesn't have circular dependence. If each foo[i] was treated as a foo_0, foo_1, foo_2 then things would be fine I assume.

I assume the always_comb solution to this problem may be difficult but would verilator be able to work around the dependence if each iteration was in a generate loop so that the code generation stage could unroll it?

logic [NUM_FOO-2:0] select [NUM_FOO-1:0];
logic foo [NUM_FOO-1:0];
generate
  for(i = 0; i < NUM_FOO; i++) begin
    always_comb begin
      foo[i] = { /* default logic goes here which could be complex */ };
      for(int previous = i-1; previous >= 0; previous--) begin
        if(select[i][previous]) begin
          foo[i] = foo[previous];
          break;
        end
      end
    end
  end
endgenerate

Replies (1)

RE: verilator unpacked dimension signal dependency without circular logic error - Added by Wilson Snyder over 2 years ago

It's a medium project, if it was easy it would have been done. :)

The two routes are to either teach the ordering code how to understand array references when they are all mutually exclusive (e.g. constant indicied), and the other is to add a new optimization which removes the array entirely by substituting uniquely named signals. The latter will perform better. If you're willing to start on making a patch for either we can discuss the relative merits.

    (1-1/1)