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Building emulator using verilator

Added by Abdullah Raza Khan over 1 year ago

I know we can create the c++ model of hardware in verilator. If I have generated the obj_dir after passing the small_riscv.v file to verilator and get a c++ model in binary. Is it possible to use binary files(e.g elf) to test your system? What I am asking is emulator scenario in which you created basic riscv and passing the elf file to verilator output. Thanks


Replies (1)

RE: Building emulator using verilator - Added by Wilson Snyder over 1 year ago

You mean load an elf into a simulated CPU? Yes, that would work, as it would with most Verilog simulators. However writing the appropriate code to do the loading into a simulated memory (or real memory) is your responsibility, again as with other simulators.

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