Using verilog configurations with verilator
We want to use verilog configurations to bind different instances of one of the modules.
Does verilator support compiling same module with different set of defines in two different libraries ?
e.g. - compile mod_m.sv to mod_0_lib with +define+mod0 compile mod_m.sv to mod_1_lib with +define+mod1
Then use this verilog configuration file to bind them on different instance
config top_cfg; design worklib.top; instance top.mod_0_u use mod_0_lib.mod_m; instance top.mod_1_u use mod_1_lib.mod_m; endconfig
No, but you can just make a top.v file with
`define FOO bar `include "mod_1.v" `define FOO baz `include "mod_2.v"
Thanks for the quick response . Our intent is to compile the same module with different defines set. In your example did you mean to say include the same .v file again i.e. mod_m instead of mod_1.v/mod_2.v ?
You need something to instantiate the model. In that case
mod1.v: `define MOD mod1 `include mod.v mod2.v `define MOD mod2 `include mod.v mod.v module `MOD; ...
This will work with any simulator.