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Getting a list of module and SystemVerilog interface dependencies

Added by Hayden Roche almost 2 years ago

My team and I have been working on getting a list of the module and interface dependencies of a given Verilated module. For example, if we run Verilator on a module A, and that module instantiates a module B and an interface C, we would like to be able to have a list of dependencies that contains B, C. The .d files produced by Verilator almost cut it, but they don't respect generate statements. If, in our previous example, B never gets instantiated because it is inside a generate block that doesn't trigger, B will still show up in the .d file. We have given vhier a shot, but it doesn't work with our SystemVerilog syntax. We are able to get this list by looking at the Verilated cpp file (e.g. VA.cpp, in the case of our example module A) and looking for comments of the form // ALWAYS/INITIAL/etc. at some_path_to_an_sv_file.sv:some_line_number_in_that_file. If B is never instantiated, it won't show up in a comment like this in the .cpp, unlike the .d file.

So, here are our options, as they seem to me:
  • Modify Verilator to produce a list of interfaces and modules that are actually instantiated as one of its outputs.
  • Parse the .cpp file as I've done. This works but is reliant on a pretty obscure fact of this file that could easily change with subsequent versions of Verilator.
  • Parse the .deadModules.tree file, which one of my colleagues has done, using --dump-tree --dump-treei 100.

Option 1 seems like the best way to go, but I have no experience with the Verilator source code. I am willing to pursue it, but am curious what other solutions, if any, are out there before I go down that path. If responders think that first option is the way to go and would like to help me through this process, do let me know. :)


Replies (14)

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

I assume when you say you tried vhier, you don't mean there's a literal syntax problem as it should be able to handle everything Verilator can, but rather the problem is it doesn't remove generates. (If it gives a syntax error that is probably a bug.)

Verilator must include even non-needed for generate files in the .d as they are parsed and in theory though unlikely they could have defines that modify later parsing, so again in theory could change the output. Presumably what you really care about is only files with used "module" statements.

There's another option which is to parse the --xml output. This lists the filename (indirectly) of every statement which then can give you the information you want, e.g. look for <module then that line's fl, then the <file associated with that id.

If you'd like something cleaner/simpler I'd suggest expanding the --xml output to include whatever output you'd want, as this will help out others that later need it. Ideally it would be great to list everything "vhier --xml" gives, assuming that output is sufficient for you.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

Hi Wilson, I am Hayden's colleague and would want to elaborate on a few things.

The syntax that doesn't work for us in Vhier (but works in Verilator) is of the type "interface_name interface_inst_name;". The absence of parentheses bothers Vhier, but Verilator works fine. Also we think that Vhier is not going to be of help because, quoting from the verilog-perl man-page,
With Verilog::Netlist how do I resolve signal widths that include parameters down to constants?

Unfortunately parameter resolution is part of elaboration. Verilog-Perl doesn't do elaboration as it requires a good fraction of a complete simulator implementation. Many applications can work around this limitation, if yours still requires elaboration you're stuck with using Verilator or the VPI, see the sections above.

We can kind of get the needed sub-modules list by post processing the *deadModules.tree file but it is slightly sub-optimal. As far as I understand, the tree file doesn't contain file names, and the module name has resolved parameters appended to the original name.

I was able to write a quick AST Visitor and update Verilator.cpp to call it after the deadifyModules step to write out the list of modules (with their origname and filename), which seems to be pretty much what we are looking for. It will be nice to get this feature into Verilator if it is possible. Would appreciate your help in providing guidance around how to add this feature. Does it have to be a command line argument based? Is there another place where this information can be output? etc.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

Your approach makes sense. Unless it doesn't work for some reason (why), could you please make your visitor output in something that is close, ideally a superset, of the vhier -xml format? That gives a nice migration path, and that format I know represents what a lot of people need/want over the years. Then if you could post a bug requesting merging that patch, after any needed review I'll be glad to merge and maintain it.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

Hi, Thanks for the reply. So the below is what I plan to do. Kindly let me know if you have any comments or concerns.

  1. Add an option --trimmed-module-files that will generate a trimmed_module_files.xml file in the output directory
  2. The file list will comprise of used modules and interfaces only. Packages or includes will not be listed.
  3. The xml output would be vhier like with modules/interfaces listed in reverse compilation order. An e.g. is given below
<verilator>
 <trimmed_module_files>
   <file>test/testbench.sv</file>
    <file>src/dut.sv</file>
     <file>src/dut_if.sv</file>
     <file>src/submodule.sv</file>
 </trimmed_module_files>
</verilator>

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

I'd suggest the switch be --xml-hier.

How is your trimmed_module_files different from normal vhier's module_files?

If there's something that module_files has that you don't want seems better to put it in the XML and you then ignore those lines downstream.

I had forgotten vhier doesn't quote the filenames we should fix that by using a bit from both formats.

How does this look?

  <?xml version="1.0" ?>
  <!-- DESCRIPTION: Verilator output: XML representation of hierarchy -->
  <verilator_xml>
    <files>
      <file id="d" filename="input.vc" language="1800-2017"/>
      <file id="f" filename="v_hier_top.v" language="1800-2017"/>
      <file id="g" filename="v_hier_sub.v" language="1800-2017"/>
    </files>
    <module_files>
      <file id="f" filename="v_hier_top.v" language="1800-2017"/>
        <file id="g" filename="v_hier_sub.v" language="1800-2017"/>
    </module_files>
    <cells>
      <cell fl="f1" name="v_hier_top" submodname="v_hier_top" hier="v_hier_top">
        <cell fl="g2" name="sub" submodname="v_hier_sub" hier="v_hier_top.sub">
        </cell>
      </cell>
    </cells>
  </verilator_xml>

Note to print the <files> and <file lines you should just call existing functions.

While you didn't ask for cell information it's the input that is used in determining module_files so is good to have for debug, and allows this new output to replace vhier.

For reference, your proposal was this:

  <verilator>
   <trimmed_module_files>
     <file>test/testbench.sv</file>
      <file>src/dut.sv</file>
       <file>src/dut_if.sv</file>
       <file>src/submodule.sv</file>
   </trimmed_module_files>
  </verilator>

For reference, vhier.xml looks like this:

  <vhier>
   <cells>
    <cell name="v_hier_top" submodname="v_hier_top" hier="v_hier_top">
      <cell name="sub" submodname="v_hier_sub" hier="v_hier_top.sub">
      </cell>
    </cell>
   </cells>
   <module_files>
     <file>verilog/v_hier_top.v</file>
      <file>verilog/v_hier_sub.v</file>
   </module_files>
   <input_files>
    <file>verilog/v_hier_sub.v</file>
    <file>verilog/v_hier_top.v</file>
   </input_files>
  </vhier>

For reference, Verilator --xml looks like this:

  <?xml version="1.0" ?>
  <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
  <verilator_xml>
    <files>
      <file id="d" filename="input.vc" language="1800-2017"/>
      <file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
    </files>
    <netlist>
      <module fl="f6" name="t" topModule="1">
        <instance fl="f18" name="cell1" defName="mod1">
        </instance>
      </module>
    </netlist>
  </verilator_xml>

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

The biggest difference with Vhier is that the output will contain trimmed list of modules and interfaces, i.e. those modules that get optimized away because of generate statements (essentially deadModules) won't show up in the list. Hence the trimmed part in the name. About the output format I was comparing against the vhier's --module-files options which, on a toy example that I had, looked like the one I had posted. Lastly I just built the latest Verilator and I don't see any xml option (tool reports back with "Invalid option: --xml"). So I am a bit confused on that part in the last example above.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

I just went through the source again to check about the xml format you mentioned and came across the undocumented --xml-only option. I guess this is the one you are talking about. It is really good and actually contains pretty much everything that we want. The only thing that is missing is the original module name in the module tag. It is possible to derive that from the defName (parameters are appended with double uncderscore), but would be really nice to have origname present right there. Apart from that I don't think we need anything else. Would like to know your thoughts on including the origname in the module tag.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

Ah --xml-only should have been documented, it started off experimental then forgot to upgrade it. Fixed in git.

Adding origname makes sense, would you like to provide a patch to V3EmitXml.cpp? Suggest dump it on the three that have it, AstNodeModule, AstVar and AstCell.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

I can definitely provide the patch to output origname. Infact, if it is fine with you, I think the output xml should have a module_files section that contains the list of used modules and interfaces files. Will save post processing the xml if the information is right there. I can add a ModuleFiles visitor that gets called in the emitXml function after Fileline::fileNameNumMapDumpXml portion.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

Modules can be identified with just a "grep '<module'" so doesn't seem worth duplicating them.

In contrast the cell report described earlier is harder to recreate as have to recurse all modules and cells, so I think if anything that's more useful.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

I have attached the git patch for the origname change. Apologies if this is not the right way to provide the patch. In that case do please let me know how to get that across to you.

About the cell report change and module files list change, I am definitely interested in implementing that, but will have to find time for it. If it is urgent, it is not best to rely on me to provide that feature.

Thanks & Regards

origname.patch View (1.22 KB)

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Wilson Snyder almost 2 years ago

Great! I called it origName to match the caps of destName.

Pushed to git towards 4.008.

RE: Getting a list of module and SystemVerilog interface dependencies - Added by Kanad Kanhere almost 2 years ago

I have attached the patch for the hier changes to --xml-only option. The V3EmitXml.cpp has been updated to output the module_files XML section and the cells XML section. I also updated the t_xml_first test and the t_xml_tag test and verified that it works. Kindly have a look. Thanks!

hier_xml.patch View (6.15 KB)

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