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Set timescale in model at runtime (ie. before first eval())?

Added by Richard Myers about 1 year ago

Hi,

I've made a dynamic library from a Verilated model. The calling program calls the model at each time step, which is passed in (ie: 10.0e-9). Is there a way to override the timescale and resolution settings in the verilated model after it is instantiated? I want the calling program to be able to set the timescale of the model so that waveform dumping is accurate (not tied to the Verilog `timescale directive).

Is it possible?

Thanks, Richard


Replies (4)

RE: Set timescale in model at runtime (ie. before first eval())? - Added by Wilson Snyder about 1 year ago

See VerilatedVcdC::set_time_unit and set_time_resolution, and the helper doubleToTimescale.

RE: Set timescale in model at runtime (ie. before first eval())? - Added by Richard Myers about 1 year ago

Hi,

I have a double with the time step, so would prefer to avoid the text conversion. I could do it and then call the functions (methods?) you referenced, but if there's an easy way to modify m_timeRes directly, then that would be ideal. Alternatively, I would love to use the doubleToTimescale method, but it's apparently not part of VerilatedVcdC (??). I tried something like this...

std::string timescale = tfp->VerilatedVcdC::doubleToTimescale(delta_t);
tfp->VerilatedVcdC::set_time_unit(timescale);
tfp->VerilatedVcdC::set_time_resolution(timescale);

got an error ...'doubleToTimescale': is not a member of 'VerilatedVcdC' I can't seem to do this either:

tfp->VerilatedVcdC::set_time_unit(doubleToTimescale(delt));

And, in any case, the set_time_unit and set_time_resolution functions affect the VCD file header, but not the time steps in the VCD waveforms. #N still increments by 1ns, and my 20Mhz clock is 500MHz. I'm setting the timescale in Verilog to 25ns / 25ns, and using the functions. I don't necessarily want 25ns; I'm just trying to understand how it works.

I think what I really want to do is to usurp the timescale setting in the simulation engine before time 0, right after instantiation. It would seem that the VCD waveform dumping module would then get it from the simulation engine ... but I don't understand how it's all put together, so ...

I'm not a C++ guy, in case that's not obvious by my boneheaded questions. So much about C++ is a mystery to me ...

Is there any way to change the timescale of the Verilated model right before simulation starts?

Thanks, Richard

RE: Set timescale in model at runtime (ie. before first eval())? - Added by Wilson Snyder about 1 year ago

You'd call tfp->set_time_unit(timescale). It's in VerilatedVcd, which is the base class of VerilatedVcdC.

The simulation engine itself is a cycle based simulator and has no knowledge of timescales or pound delays, so there's no way nor meaning in setting its timescale. (Well, mostly, with the exception of when printing a time it needs to know how to convert your sc_time_stamp to a value to print, this uses VL_TIME_PRECISION and VL_TIME_MULTIPLIER.

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