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Verilate SystemVerilog RTL without a top module?

Added by Justin Jones 14 days ago

I'm a new to using verilator and I am trying to use it to cross verify RTL with an architectural model. Our model is in SystemC and it takes a bunch of subsystems and connects them via bind and interfaces at the main.cpp (top level).

Let's say main.cpp only has two modules a and b. I would like to take module b and replace it with a verilated version of the RTL for module b. The issue I get is b is not a top level module and has SV interfaces as well as a port for clock and reset.

Is there a way to verilate module b on it's own and then compile and build with the rest of our Model?

Or do I need to verilate the entire Model from main.cpp?

Thanks for any help, Justin

Replies (1)

RE: Verilate SystemVerilog RTL without a top module? - Added by Wilson Snyder 13 days ago

So the problem is you want to verilate something at top with interfaces poking out the top?

Typically when doing this we'd make a new verilog wrapper file that instantiates b and de-interfaces it. Then verilate that and put it into your main.cpp.

If you do this a lot it usually can be half-automated using verilog-mode's AUTO features to make the ports (see verilog-mode FAQ), or fully automated using using e.g. Verilog-Perl or verilator --xml to determine the top level port names then having a script generate the wrapper. Unfortunately I don't have examples of those scripts I'm free to share.