Retain verilog hirarchy in c++ class hirarchy ?
A Verilator newbee question: When I specify a hirarchical verilog design with multiple modules, split in several files, is the design then always flattend to a single c++ class or is there a possibility that verilator retains the hierarchy by createing a class for each seperate module ?
Verilator keeps, adds or combines classes based on a bunch of algorithms attempting to maximize performance. For the most part the using code should not be designed to care what the result classed are (except for using verilator public, which is duscouraged).
I looking at a way where I can emulate peripherals via C functions and was reading through https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html . Is there a way to read/drive signals other than the top-module signals? Is there a possibility to define a module in C that is inside the verilog structure? Maybe define a wires and use verilator public on them? There doesnt yet seem to be a foreign language interface?
Use the DPI.
import "DPI-C" pure function void send_byte(uint8_t b); always @ (posedge clk) begin if (enable) send_byte(data); end