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Using packed struct for register definition

Added by Konrad Eisele 2 months ago

Verilator supports
typedef struct packed {
    bit [10:0]  expo;
    bit         sign;
    bit [51:0]  mant;
} FP;
I wonder where packed structs can be used: It seems it can be used instead of wire, but can it also be used to define a reg?

Replies (2)

RE: Using packed struct for register definition - Added by Wilson Snyder 2 months ago

reg is a datatype just like 'FP'. However please note this site is intended to discuss Verilator and other related features and issues, not how to learn SystemVerilog. Instead you'll be better served by one of the language tutorials, for example http://www.asic-world.com/systemverilog/tutorial.html

RE: Using packed struct for register definition - Added by Konrad Eisele 2 months ago

Ok I understand. Coming from vhdl I try to get familiar with Verilog and Verilator. Will try to get info from other forums. Thanks.

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