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Why does my module I/O signature change, even when I give the /* verilator no_inline_module */ directive?

Added by David Banas about 1 year ago

Let's say I have the following Verilog code:

module myMod (
  input  logic clk, x, y,
  output logic z
);

/* verilator no_inline_module */

always @(posedge clk)
  z <= x ^ y;

endmodule

module top (
  {I/O defs}
);

myMod blk1(...);
...

endmodule

Upon Verilation I find that I have a file: top_myMod.h.
And that file defines a class: Vtop_myMod.
That class defines a public function: _sequent__TOP__top__DOT__myMod__2, which I assume is the C++ implementation of the functionality defined in the always block of my myMod module.
Now, here's the kicker: the calling signature of that function does not match the I/O signature of my myMod module!
Instead, it looks like this:

void _sequent__TOP__top__DOT__myMod__2(Vtop__Syms* __restrict vlSymsp);

Why?


Replies (2)

RE: Why does my module I/O signature change, even when I give the /* verilator no_inline_module */ directive? - Added by Wilson Snyder about 1 year ago

Verilator does not attempt to match ports etc in the C functions as that is too slow. Instead all vars are via that sym pointer.

If you are interested in internals please see internals.txt and poke around the generated code and it should start to make sense.

RE: Why does my module I/O signature change, even when I give the /* verilator no_inline_module */ directive? - Added by David Banas about 1 year ago

Thanks, Wilson!

I will do as you suggest.

In the meantime, can you tell me what happens if there are 2 or more instantiations of myMod?
It seems like they'd overwrite each other if given the same pointer.

    (1-2/2)