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About assigning values to C++ models and getting values(VPI)

Added by Yu Kai Liang about 1 year ago

In the verilated_vpi.cpp file, the vpi_get_value and vpi_put_value methods respectively take values and assignments to the C++ model. According to the specific implementation of the code, it is known that the value and assignment of varDatap to VerilatedVpioVar. How do I change the value of the C++ model after the value and assignment of VerilatedVpioVar's varDatap? Are there detailed steps?

1.jpg View - vpi_get_value (257 KB)

2.jpg View - vpi_put_value (261 KB)


Replies (9)

RE: About assigning values to C++ models and getting values(VPI) - Added by Wilson Snyder about 1 year ago

What are you trying to do? Those internals are not something that you normally need to use, applications are expected to use the vpi_get/put_value routines instead as described in the IEEE 1800 specification.

RE: About assigning values to C++ models and getting values(VPI) - Added by Yu Kai Liang about 1 year ago

I'm working on chisel-testers, and I've traced back to its test mechanism approach to calling the vpi_get_value and vpi_put_value methods. Should you refer to the vpi_get method in vpi.h? If so, the vpi_get method still calls the vpi_get_value method.

RE: About assigning values to C++ models and getting values(VPI) - Added by Wilson Snyder about 1 year ago

Please take a step back from the internals, what is broken or what problem are you having?

RE: About assigning values to C++ models and getting values(VPI) - Added by Yu Kai Liang about 1 year ago

I don't know how to affect the value of the specified signal in C++ model after calling the vpi_put_value method.

RE: About assigning values to C++ models and getting values(VPI) - Added by Wilson Snyder about 1 year ago

I assume by "in C++ model" you mean affect a signal in Verilog that has been Verilated into C++.

First, check there are no errors returned by the VPI call. Assuming not, and the value is not changing, you probably forgot to add the appropriate verilator_public_flat_rw or similar comments into your verilog model, please see the documentation.

RE: About assigning values to C++ models and getting values(VPI) - Added by Yu Kai Liang about 1 year ago

Yes, my problem is after calling the vpi_put_value method, how to affect a signal in Verilog that has been Verilated into C++. In other words, I traced from the chisel-testers to the vpi_put_value method will affect a signal in Verilog that has been Verilated into C++. But I don't know how to affect a signal in Verilog that has been Verilated into C++ and what is the internal structure of the C++ model? Can you give me some advices? Thank you.

RE: About assigning values to C++ models and getting values(VPI) - Added by Wilson Snyder about 1 year ago

See the "VPI" section of the documentation. You should not need to look at or understand the C++ internal code to get this working (unless of course you want to make improvements/fixes which would be appreciated!).

RE: About assigning values to C++ models and getting values(VPI) - Added by Yu Kai Liang about 1 year ago

Can you refer to the "VPI" section of the documentation as the following URL? If so, this introduction seems to be too little. If not, please send me the website. Thank you very much! https://www.veripool.org/projects/verilator/wiki/Manual-verilator#VERIFICATION-PROCEDURAL-INTERFACE-VPI

RE: About assigning values to C++ models and getting values(VPI) - Added by Wilson Snyder about 1 year ago

That is the link, yes. The assumption is you are already familiar with the general VPI as described in IEEE and other simulator-agnostic tutorials. If you find information missing please consider submitting documentation patches.

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