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Simulation slow down due to a large new block that's idle

Added by Stan Sokorac over 1 year ago

I've recently added a large new block into the simulation... and even though the block is completely idle in tests, the simulation speed dropped to 30-40% of what it used to be. The new block is definitely quite large, but I was hoping that Verilated code would be able to skip calculations of logic that isn't changing... I've even tried tying off the clock to 1'b0, but it had no effect. Maybe it's my lack of understanding of how verilated code works -- maybe the lack of clock and activity doesn't help as everything gets evaluated all the time? I'm hoping that I'm wrong and that there's something I can do to limit the effect of the new logic when it's not active.

Any hints or tips?


Replies (1)

RE: Simulation slow down due to a large new block that's idle - Added by Wilson Snyder over 1 year ago

If the logic is all on a clock and the clock is disabled you should not see a large change. Make sure there aren't any UNOPTFLAT messages, once one exists it may get much slower.

You can use the --prof-cfuncs option along with gprof to see where the performance issue is coming from.

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