eval() multiple times on same clock edge
I have a hardware design that needs to make a memory request at most 3 times per cycle. I have generated c++ for my design. Part of the design is a black box verilog module that simply exposes signals for memory requests that some other non verilator related c++ code will attempt to service. My issue is that in cases where I need to do more than 1 memory accesses, the 2nd (or 3rd) access depends on the result of the first (or 2nd) access which needs to be evaluated. Is there anyway I can make the first access, call evaluate, then call evaluate again within the same cycle with the extra new addition to the state of the machine? I access signals using the /* verilator public */ methodology. Thanks
RE: eval() multiple times on same clock edge - Added by Wilson Snyder 10 days ago
Perhaps declare a DPI import function. Then create an always sensitivity list (real or fake) and Verilator will then know how to schedule. Ideally if you can pass all signals through the import you will not need public (making a faster and simulator portable model).
always_comb fake1 = dpiimp1(insig); always_comb outsig = dpiimp2(fale1);