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About signal naming

Added by Rafael Tonetto 12 months ago

I'm new to Verilator, and I have a doubt.

After synthesizing a complex circuit, I noticed that the C++ code has a lot of signals with the strings "_GEN" and "_T" concatenated to some of the variable names. What's the meaning of those variables? Are those variables flip-flops or wires?


Replies (1)

RE: About signal naming - Added by Wilson Snyder 12 months ago

Verilator doesn't add _GEN. Perhaps you mean genblk which is the relatively standard across simulators name for a otherwise unnamed begin block within generate statements.

Verilator doesn't add _t to signal names. Some internal non-signals use _t to mean a typedef.

internals.txt has some info on naming, if you're curious (as in general to just use Verilator none of this naming should matter).

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