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Verilator detect problem of '@'

Added by Zhiyuan Ning 5 days ago

I write a .sv task inside an interface like: task receive ();

assert property (@(posedge data)) ;

endtask

When I try to convert it into SystemC, the verilator throws an error that: %Error: SFQ_PKG.sv:33: syntax error, unexpected ')', expecting TYPE-IDENTIFIER

When I change the code into: task receive ();

@(posedge data) ;

endtask

The verilator also gives me an error that %Error: SFQ_PKG.sv:33: syntax error, unexpected '@'

Could I know what is going wrong and how could I modify it?


Replies (3)

RE: Verilator detect problem of '@' - Added by Wilson Snyder 5 days ago

Verilator doesn't support arbitrary event expressions, sorry.

Specifically, tasks can't have time pass and generally you'll need to refactor such tasks to look like synthesizable code.

RE: Verilator detect problem of '@' - Added by Zhiyuan Ning 5 days ago

How could I refactor such tasks (time pass) to look like synthesizable code? Could you give me an example?

RE: Verilator detect problem of '@' - Added by Wilson Snyder 5 days ago

  task cycle;
     d = 20;
     @(posedge clk);
     d = 30;
     @(posedge clk);
  endtask
  always @ (trigger)
    cycle;

Change to how you would write this in synthesized code e.g. using a FSM

  integer state;  initial state = 0;
  always @ (posedge clk) begin
     case (state);
         0: if (trigger) begin state = 1; d = 20; end
         1: begin state = 0; d = 30; end
     endcase
  end
    (1-3/3)