Any chance to use Verilator together with Icuras?
With Verilator to compile the DUT part and have Irucas handle the testbench which might be UMV based.
Verilator has plans to add "embedding" of a model in another simulator, but this is not ready yet (there is another old thread on this here).
Anyhow, Icarus does not support UVM and AFAIK supports less SV than Verilator.
... "Verilator has plans to add "embedding" of a model in another simulator"
This is exactly how I use Verilator with VCS. I basically create a Verilog wrapper around the Verilated model and call eval() via DPI whenever any of the inputs change. Output changes as a result of the eval call are detected and passed back via DPI to update the pins on the wrapper.
I wrote a noddy tool called 'wrapgen' which builds this code (one .cpp file and one .sv file - both ends of the DPI calls) automatically from the output of verilator and then wraps it again with the original RTL DUT along side and a big knife switch on the I/O so I can run my TB in RTL or verilated mode, just by flicking the switch, which is connected to a plusarg on the simv exe command line.
./simv +test=mytest +verilated // Test with the Verilated DUT ./simv +test=mytest // Use the RTL DUT (for signoff, and GUI runs)
It would be great if we could add something similar as a backend process in the verilator generated makefile. I'll see if I can upload an example design to illustrate the approach a bit more clearly....
Great! There's been a lot of progress in the last month or so, with --protect-lib added etc, please see bug1572. I'm sure Todd would welcome help in testing and improving this process.