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A strange code generated from parametric module.

Added by Slava B 6 months ago

Hello,

I was asked to convert a big Verilog project to SystemC. I'm a novice in Verilog and cannot explain the resulting code. I've minimized scenario to a few lines:
module arbiter #(
    parameter VCD_PORT_NUMBER = 3
)
(
    input clk,
    output reg [VCD_PORT_NUMBER-1:0] in_ip2bus_ack,
    output reg [(VCD_PORT_NUMBER*32)-1:0] in_ip2bus_data
);
    always @ (posedge clk)
        begin
            in_ip2bus_ack = 3'b0;
            in_ip2bus_data = 96'b0;
        end
endmodule
The resulting translation is:
SC_MODULE(Varbiter) {
  public:

    sc_in<bool> clk;
    sc_out<uint32_t> in_ip2bus_ack;
    sc_out<sc_bv<96> > in_ip2bus_data;
...
}    
The code generated for in_ip2bus_data looks reasonable. But for in_ip2bus_ack I'd expect sc_out<sc_bv<3> >. Why did I receive sc_out<sc_bv<96> >? It will mislead readers. Thanks!

Replies (2)

RE: A strange code generated from parametric module. - Added by Wilson Snyder 6 months ago

I assume what you really mean is you got a uint32_t. Verilator does this because it's several times faster than using bvs. See the "CONNECTING TO SYSTEMC" part of the manual.

RE: A strange code generated from parametric module. - Added by Slava B 6 months ago

Thanks for reply, Wilson. I'd like to understand why Verilator converts verilog's 3-bit port into 32-bit port in SystemC.

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