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Verilator should have converted inout ports to input/output pairs.

Added by Slava B 11 months ago

Hi,

As far as I understand from the documentation, Verilator should convert inout ports to input/output pairs. Is it correct? It did not happen in my case. These ports were converted to sc_inout<bool>. Should I use a command line switch to enable this feature?

Regards, Slava


Replies (2)

RE: Verilator should have converted inout ports to input/output pairs. - Added by Wilson Snyder 11 months ago

The documentation should be updated, currently what it does for __en etc is only in the internals not top pins. One workaround is to make a wrapper module that does the conversion.

E.g. module wrap;

input foo_in;
input foo_en;
output foo_out;
wire foo = foo_en ? foo_in : 'z;
wire foo_out = foo;
    (1-2/2)