Project

General

Profile

[logo] 
 
Home
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Conversion of a hierarchical design

Added by Slava B 11 months ago

Hi,

First of all, thanks for the great tool. I took a big design, written in Verilog, and converted it to SystemC in a few clicks. Perfect!

I asked Verilator to convert the design's top file. It converted this file and all the modules used in this top file. However, Verilator converted the hierarchical design into one flat SystemC file. From a debugging point of view, it is hard to deal with such a flat design. Is it possible that Verilator will retain the hierarchical structure of the Verilog's project and create .cpp/.h files for each .v?

Regards, Slava


Replies (3)

RE: Conversion of a hierarchical design - Added by Wilson Snyder 11 months ago

Verilator basically compiles into SystemC, versus just translating to something debuggable.

However you can use "--public" and it will more closely match the original code. This may run significantly slower, might expose bugs, and is not recommended for production use.

RE: Conversion of a hierarchical design - Added by Slava B 11 months ago

I understand your point. If the compiled design and test-bench start working properly from the fist moment, everything is OK. However, if something is not working as expected, you have to have an option to debug the issue. I'll definitely try "--public" in these cases.

Thanks for help! Slava

RE: Conversion of a hierarchical design - Added by Slava B 11 months ago

By the way, sw debugging became less relevant when I found out that it is possible to add internal Verilog signals to .vcd files...

    (1-3/3)