![]() |
Home |
About/Contact |
Major Tools |
Dinotrace |
Verilator |
Verilog-mode |
Verilog-Perl |
Other Tools |
IPC::Locker |
Parallel::Forker |
Voneline |
General Info |
Papers |
Added by Slava B over 1 year ago
Hi,
I was curious why single-bit signals are represented in verilated SystemC code as:
VL_SIG8(signal_name, 0,0)
Such a representation is confusing when showed in waveform viewers.
Thanks, slava
It's because that is an order of magnitude faster. See the Verilator manual for options on representing SC signals.