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Using vcs to simulate design with multiple verilated uC cores?

Added by Oleg Rodionov 4 months ago

In my vcs simulation model, for certain, simulation content, I see majority of simulation time spent in the microcontroller(arc) cores.

I have two questions: 1. Do you think I can improve overall performance by incorporating 4 verilated uC cores into verilog design in vcs?

2. What's the best performing approach to integrate verilated cores back into verilog design?

Note, I was able to verilate the core and run standalone simulation.


Replies (9)

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Todd Strader 4 months ago

I don't know the answer to #1, but for #2 you should be able to use this in-progress feature once it is ready: https://www.veripool.org/issues/1490-Verilator-Add-an-option-to-create-a-DPI-protected-library

It's not really the intended use case, but it will do what you are suggesting. The branch is very much in process so I would be wary of picking it up just yet unless you really like living life on the edge. Of course, you can do the same thing manually (i.e. verilate your uC core, wrap it in DPI calls and instantiate the verilog wrapper in the design you give to vcs). But that's what --dpi-protect is attempting to do for you.

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Oleg Rodionov 4 months ago

Awesome! Thank you Todd. I will check it out and report back. If it works good enough to re-run the same simulation, I might be able to report back performance results as well

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Oleg Rodionov 4 months ago

Todd, I downloaded the link. Verilator version doesn't have all the familiar makefiles and configuration. How do I go about building and running this development version?

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Todd Strader 4 months ago

So you're a void-the-warranty kind of person? I respect that.

To be clear, this branch is passing CI including a test I added for --dpi-protect. However, the new feature is far from completely tested and will require some refactoring before it can be landed.

But if you're still determined to push ahead, I think what you're missing is probably 'autoconf'. See README.pod for all the hairy details, but the .tgz includes the results of autoconf so if you're used to building from the tarball you probably haven't run into that before.

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Todd Strader 4 months ago

Also, I'm not sure how vcs will accept DPI objects. By default --dpi-protect will produce a static library (.a) but if you pass --dpi-protect-shared to Verilator you'll get a shared library (.so). If you make it this far and can experiment to find out which of these ways (or both) vcs accepts DPI objects that would be handy to know.

And hopefully it goes without saying, if you find any problems with --dpi-protect please report back as I'm actively working on test cases, etc.

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Oleg Rodionov 3 months ago

I was able to replace verilated uC core into my RTL design and simulate with VCS. I did following steps: 1. Verilate RTL core into systemC design 2. Run syscan tool on verilated systemC design 2. Build mixed vcs simulation model with SystemVerilog + SystemC verilated core.

Results were not good :( About 20% slower.... May be due to "-sysc" flag that made simulated mixed-mode instead of pure systemverilog

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Wilson Snyder 3 months ago

Interesting, but not unlikely as lots of baggage with SystemC. Would you be able to run the --dpi-protect benchmark experiment too?

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Oleg Rodionov 3 months ago

Todd, I was able to compile my core with -dpi-protect flag. I do see static library being generated, but I don't see a verilog wrapper generated. Any ideas?

RE: Using vcs to simulate design with multiple verilated uC cores? - Added by Todd Strader 3 months ago

I'm not entirely sure, but it sounds like you're still on my development branch as we renamed the feature to --protect-lib somewhere along the way. This has been landed in the trunk now, so I would suggest pulling the latest from GitHub and trying that. Note that the SV wrapper will be generated in obj_dir/ or wherever you point -Mdir.

Also, please note that the performance of --protect-lib still needs some attention: https://www.veripool.org/issues/1520-Verilator-Improve-protect-lib-performance

At present there is a good amount of unnecessary copying and eval()ing going on.

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