Testbench patterns to run N cycles ?
as I understand from the example sim_main.cc replaces the testbench. The main loop stops when it receives the "finish" signal from the module.
How would I approach the testbench when the e.g. full adder module (http://referencedesigner.com/tutorials/verilog/verilog_14.php ) does not have the finish signal built in?
i.e. how would I stop main loop after N cycles?
RE: Testbench patterns to run N cycles ? - Added by Wilson Snyder 3 months ago
It finishes when there's a $finish, that's not really a signal.
Anyhow the example you point to should have s $finish after the # 40 in the test bench.
Note this isn't a Verilator-friendly example, as the test bench provided for Verilator would need to be in C++, or a FSM in Verilog. Also $monitor isn't supported. I don't have a great alternative page, maybe look at https://github.com/ZipCPU/wbuart32
Please report back if you look for and find a good alternative tutorial that is Verilator friendly.