Basic questions: Multiple modules and using "#"
I want to play with some simple modules and signals and tried this:
module half_adder(x,y,s,c); input x, y; output s, c; xor(s,x,y); and(c,x,y); endmodule module our; reg[1:0] in; wire[3:0] out; initial begin $display("Start."); in = 2'b00; #5 $display("input: %b", in); $finish; end endmodule
1) Can I write several modules in one .v file? If not how would I structure these best?
2) How would I put a simple time model (using # equivalent) into the sim?
1) Yes, you can put multiple modules per file.
2) You'd write this in C code, for example in = 0; then make time pass and call topp->eval(), then print the value.
However if you're just doing this to learn Verilog you might want to consider using Icarus Verilog instead, as then most of the examples you find online will work directly as written.