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How to set the value of a corresponding verilog parameter in the generated C++ code

Added by Ashutosh Pal about 8 years ago

Consider the following input verilog code (assuming this is top level):
module mul_abc
  (a, b, c);

  parameter width_a=8;
  parameter width_b=8;
  input [width_a - 1: 0] a;
  input [width_b - 1: 0] b;
  input [width_a+B_width- 1: 0] c;
In the generated C++ (i.e. after verilation), the parameters are replaced with their default value i.e. 8 in the above example and then there's no way to configure the value of these parameters from the C++ testbench, unlike in the verilog testbench, where you can specify the values of the parameters during instantiation of mul_abc. The generated C++ code snippet is as below:
VL_MODULE(V_mul_abc) {
  public:
    VL_IN8(a,7,0);
    VL_IN8(b,7,0);
    //char  __VpadToAlign3[1];
    VL_IN16(C,15,0);

Please advise on how the values of the parameters can be changed from the C++ testbench.


Replies (1)

RE: How to set the value of a corresponding verilog parameter in the generated C++ code - Added by Wilson Snyder about 8 years ago

Sorry, parameters can change the code that is compiled into the model (generate for/generate if) in addition to the data types, and there is no way to translate that functionality to C++, nor can I think of any way to ever do it short of a just-in-time compiler.

    (1-1/1)