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Efficient Usage of Verilog-Parameters

Added by Stefan Wallentowitz almost 9 years ago

Hi,

is there any efficient way of using verilator parameters? For my SystemC-Module I would like to instantiate multiple blocks of a module, each with a parameter. My solution: I make the parameter explicit via a register or wire. Then I inherit from the SystemC module and add a constructor that has the parameter and sets this wire.

Is there a better way, that I miss for the moment? Since my approach has an impact on my original verilog code, it would be nice to have such an option in verilator.

Thanks, Stefan


Replies (8)

RE: Efficient Usage of Verilog-Parameters - Added by Wilson Snyder almost 9 years ago

Sorry, there's no other way to do this, and it's rare enough that I don't want to add it at this time, but if you want to make a patch I'll consider it.

IMHO, if the parameter can be made a wire it probably should be a wire. The general intent of parameters is to vary the width and size of things. (And if it does need to vary the size, then it must be known at compile time.)

RE: Efficient Usage of Verilog-Parameters - Added by Calvin Maree almost 2 years ago

Hi Wilson,

Sorry I can see this thread is very old..

Can a parameter value be accessed from the cpp code? I feel its quite an important feature to support, currently I cannot see how to get around this writing my testbenches..

Regards Calvin

RE: Efficient Usage of Verilog-Parameters - Added by Wilson Snyder almost 2 years ago

Public parameters are supported. I updated the docs, as whenever that changed it was forgotten.

RE: Efficient Usage of Verilog-Parameters - Added by Ciro Santilli almost 2 years ago

Would it be feasible in principle to implement parameters with C++ integer template arguments?

Would that be a very difficult task?

RE: Efficient Usage of Verilog-Parameters - Added by Wilson Snyder almost 2 years ago

Would it be feasible in principle to implement parameters with C++ integer template arguments?

Do you mean have the wrapping C code set parameters? Even ignoring Verilator's implementation, that's completely impossible given how verilog parameters work with elaboration.

RE: Efficient Usage of Verilog-Parameters - Added by Ciro Santilli almost 2 years ago

Yeah, something like:


module counter #(
    parameter BITS = 1
)

map to:

template<int BITS>
class Vcounter {
};

and then some insane template metaprogramming.

Oh well :-)

RE: Efficient Usage of Verilog-Parameters - Added by Stefan Wallentowitz almost 2 years ago

Yeah, that is not possible, because the parameters are already evaluated during "verilation" (verilog->c++). After that they are not visible anymore. I had a look at it when working on the -G command line switches to set parameters and changing them to be dynamic is a very complex endeavor. For example the size of signals is not known during the verilator run then etc. A lot of preparation changes on the code generation would be required to support this feature.

Cheers, Stefan

RE: Efficient Usage of Verilog-Parameters - Added by Wilson Snyder almost 2 years ago

It's worse than that. SystemVerilog is a context sensitive language, and the parsing changes and even which files are read change based on the parameter values in play. I think it's fundamentally impossible to do this with Verilog ever, in the completely general case. (I'm ignoring some boost template metaprogramming tricks, which while they are Turing complete, can't read files and so aren't practically reasonable for implementing the entire code base of something like Verilator.)

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